AM64x SOM Hardware User Manual

Revisions and Notes

Date	Owner	Revision	Notes
25 May 2022	Noam Weidenfeld	1.0
Nov 9, 2023	Shahar Fridman	1.1	Add power consumption table
Dec 12, 2023	Josua Mayer	1.2	Update Pinout Tables: - add SoC ball names - add SoC ball numbers - update usafe by carrier for hummingboard v1.2

Disclaimer No warranty of accuracy is given concerning the contents of the information contained in this publication. To the extent permitted by law no liability (including liability to any person by reason of negligence) will be accepted by SolidRun Ltd., its subsidiaries or employees for any direct or indirect loss or damage caused by omissions from or inaccuracies in this document. SolidRun Ltd. reserves the right to change details in this publication without prior notice. Product and company names herein may be the trademarks of their respective owners.

Introduction

This User Manual relates to the SolidRun SR-SOM-AM64xx-series, which includes

• Single/Dual core ARM A53 (1.0 GHz).
• Single/Dual cores Cortex®-R5F 800 MHz processor.
• A general-purpose Cortex®-M4F 400 MHz processor.

Overview

The SolidRun’s SR-SOM-AM64xx is a low power, low-cost high performance micro system on module (S.O.M.) based on the highly integrated TI's AM64xx family of products targeting the Industrial Market Applications.

Highlighted Features

• Ultra-small footprint SOM (47x30mm) including three board-to-board connectors (250 total pins number).
• TI's AM64XX SoC: - Single/Dual core Cortex A53 up to 1.0GHz - 400 MHz Cortex-M4F subsystem processor supports real time tasks. - Up to two dual-core Cortex-R5F MCU subsystems at up to 800 MHz, integrated for real-time processing. - Safety & Security engines
• DDR4 (1.6 GHz) memory in x16 configurations supports up to 2GB and inline ECC
• Up to two 1GB Ethernet port supporting Industrial Ethernet protocols.
• Single Gigabit Ethernet interface.
• Two ports TSN GE switch.
• Industrial IO supports – CAN, RS-485 etc.
• Single PCIe Gen 2 or USB 3 interface.
• Low latency interfaces to motor control front.

Supporting Products

The following products are provided from SolidRun both as production level platforms and as reference examples on how to incorporate the SOM in different levels of integration:

• HummingBoard AM64x– A board computer that incorporates the SOM retains the same Linux distributions while adding extra hardware functionalities and access to the hardware.

Description

Block Diagram

The following figure describes the AM64xx SOM's Blocks Diagram.

Features Summary

Following is the features summary of the SOM. Notice that some of the features are pinout multiplexed (please refer to the pin mux table and the TI's AM64xx data sheets):

· Dual/Single ARM® Cortex™ A53 Processor, up to 1.0 GHz

· Dual or single dual-core Cortex R5F Up to 800 MHz

· Cortex-M4 subsystem processor up to 400 MHz

· Up to 2GByte DDR4 memory

· Up to 64 GB eight bits eMMC memory.

· OSPI/QSPI NOR Flash memory.

· I2C EEPROM.

· Up to 3 x 10/100/1000 Mbps Ethernet PHY

o Up to two gigabit Industrial Communication Subsystems e.g., ECAT, Profinet etc.

o Time stamping

o TSN

· SUB Giga modem (CC1312)

· Variety of interfaces and IO on Board-to-Board connectors.

A single 5.0V interface

Core System Components

AM64xx Sitara SoC Family

The AM64xx Sitara processors feature advanced implementation of a duad Arm® Cortex®-A53 core, which operates at speeds of up to 1.0 GHz. A general-purpose Cortex®-M4 core processor is for low-power processing and two dual-core Cortex-R5F supporting industrial protocols.

The following figure describes the AM64xx main features (For more details refer to TI’s AM64x datasheet).

Memories

The AM64xx SOM supports varieties of memory interfaces for booting and data storage. The following figure describes the AM64xx SOM memory interfaces.

DDR4

• Up to 2GB memory space.
• 16 Bits data bus.
• Up to 1600 MT/s.
• Inline ECC.

eMMC NAND Flash

Up to 64GB memory space.

• 8 Bits data bus.
• Support of eMMC5.1 Host Specification (JESD84-B51).
• HS200 SDR: 1.8 V, 0-200 MHz, 8/4-bit bus width, 200/100 MB/s
• HS400 DDR is NOT supported.
• Can be used as BOOT NVM *

Octal Serial NOR Flash (SOM)

• Supports 1/2/4 or 8-bit operation.
• Support for DDR Mode and DTR protocol.
• Programmable device sizes
• DMA NOT supported.
• In Octal-SPI and Quad-SPI mode, Mode 1, 2, and 3 are NOT supported.
• Can be used as BOOT NVM *

EEPROM (SOM)

· 1Kb EEPROM

· ON-Semi’s CAT24AA01TDI or compatible

· Address 0X50 (7 bits format)

· Stores SOM’s configuration such as MAC addresses, Memory Configuration, Serial Number etc. → Not recommended for customer data.

Micro-SD (Carrier)

· Optional on Carrier board

· Implements 4 data bits.

· SD Host Controller Standard Specification 4.10 and SD Physical Layer Specification v3.01.

· SDIO Specification v3.00

· DDR50: UHS-I 1.8 V signalling, frequency up to 50 MHz, up to 50 MBps.

· SDR104 is NOT supported.

· Can be used as BOOT NVM *

*Note – All boot configuration signals are available on the SOM connector.

10/100/1000 Mbps Ethernet Interfaces

The AM64xx SOM supports three Giga-Ethernet interfaces. One of the interfaces is connected directly to the Ethernet switch (CPSW3G) and the two others are part of the Programmable Real-Time Unit and Industrial Communication Subsystem – Gigabit (PRU_ICSSG). The following figure describes the Ethernet port interfaces.

The three Giga Ethernet PHY are TI’s DP83869:

• Low RGMII Latency
• Low Power Consumption
• Time Sensitive Network (TSN) Compliant
• IEEE1588 Support
• Cable Diagnostics
• Recovered Clock Output for SyncE
• MDI or MDIX support.

PRU_ICSSG

• Two Real-Time Ethernet ports.
• MDIO port to control external Ethernet PHY
• Time Stamping support.
• Industrial protocols used in master and slave mode, such as:

o EtherCAT®

o PROFINET™

o EtherNet/IP™

o Others

CPSW3G

• Single Giga Ethernet port
• Synchronous 10/100/1000 Mbit operation
• MDIO port to control external Ethernet PHY
• Support for Audio/Video Bridging (P802.1Qav/D6.0 and 802.1Qaz)
• Support for IEEE 1588 Clock Synchronization (2008 Annex D, Annex E and Annex F)
• IPV4/IPV6 UDP/TCP checksum offload.

Clock Chaining

The following figure describes the Ethernet reference clock configuration.

The 25Mhz clock source is the CPU’s CLOCOUT1 signal. It is connected to the CPCW3G Ethernet PHY.

ICSSG1 clock is connected to CPSW3G output clock and ICSSG2 is connected to ICSSG1 clock.

Note – Clock need to be active before reset signal is de-asserts

AM64xx External Interfaces

General

The SOM incorporates three Hirose DF40 board-to-board headers.

The selection of the Hirose DF40 is due to the following criteria:

· Miniature (0.4m pitch)

· Highly reliable manufacturer

· Availability (worldwide distribution channels)

· Excellent signal integrity (supports 6Gbps)

o Please contact Hirose or SolidRun for reliability and test result data.

· Mating height of between 1.5mm to 3.0mm. AM64xx headers are fixed, the final mating height is determined by carrier implementation

Supported Interfaces - Main

PCIe & USB3

The AM64xx supports a single Ser/Des interface. The Ser/Des can be configured as a PCIe or a USB3.0 interface. The following figure describes the optional Ser/Des configurations.

The PCIe main features are:

· Ser/Des is configured as PCIe.

· On board coupling capacitors for TX and CLK.

· PCIe clock is generated on the AM64xx SoC.

· Single PCIe lane up to 5.0GT/lane.

· Gen2 (5 Gbps 8/10-bit encoding), and Gen1 (2.5 Gbps 8/10-bit encoding) with auto-negotiation.

· Compliant to PCI-Express® Base Specification, Revision 4.0 (Version 0.7).

· PHY Interface for the PCI Express Architecture, Version 4.2 compliance.

· Supports Spread Spectrum Clocking in Transmitter and Receiver.

USB main features are:

· Ser/Des is configured as USB 3.1.

· Universal Serial Bus 3.1 (USB) subsystem with integrated USB2.0 PHY

· Dual-Role Device (DRD) capability

· Compliance with USB 3.1 Gen1 Specification

· Support of Peripheral (aka Device) mode at Super Speed (SS at 5 Gbps), High Speed (HS at 480 Mbps), and Full Speed (FS at 12 Mbps)

· Support of Host mode at Super Speed (SS at 5 Gbps), High Speed (HS at 480 Mbps), Full Speed (FS at 12 Mbps), and Low Speed (LS at 1.5 Mbps)

· ECC on internal RAMs

NOTE – USB 2.0 is always available even if the Ser/Des is configured as PCIe.

UART

The AM64xx SOM can support up to 4 UART interfaces. The following figure describes the UART interfaces.

The UART interfaces main features are:

· UART 0 supports TX, RX, CTS and RTS. After POR it is used as terminal.

· UART 2 supports TX, RX, CTS and RTS.

· UART 3 Supports TX, RX, CTS and RTS.

· UART 4 support TX, RX

· RS-485 external transceiver auto flow control support.

· Baud rates up to 3.6 Mbps. Auto-baud between 1200 bits/s and 115.2 Kbits/s.

· Flow control: Hardware (RTS/CTS) or software (XON/XOFF).

· Optional multi-drop transmission.

Note – The UART signals are multiplexed with other functional options. Refer to the Pin MUX tools for optional functionalities.

eSPI

The AM64xx SOM supports two eSPI interface. The following figure describes the eSPI interface.

· Single HW chip select nSS0.

· Master/Slave configurable.

· Serial clock with programmable frequency, polarity, and phase for each channel.

Note – The eSPI signals are multiplexed with other functional options. Refer to the Pin MUX tools for optional functionalities.

I2C

The AM64xx SOM supports up to two I2C Interfaces. The following figure describes the I2C interfaces.

The I2C main features are:

· I2C-0 is connected to the SOM EEPROM and BtB connector.

· I2C-1 is available on the connector by default.

· Pull-up resistors assembled on SOM.

· Multi-master operation.

· In Standard mode, I2C supports the data transfer rates up to 100 kbits/s.

· In Fast mode, data transfer rates up to 400 kbits/s can be achieved.

Note – The I2C signals are multiplexed with other functional options. Refer to the Pin MUX tools for optional functionalities.

uSD

The uSD supports the following features:

· AM64xx’s MMC-1.

· Optional on Carrier board

· Implements 4 data bits.

· SD Host Controller Standard Specification 4.10 and SD Physical Layer Specification v3.01.

· SDIO Specification v3.00

· DDR50: UHS-I 1.8 V signalling, frequency up to 50 MHz, up to 50 MBps.

· SDR104 is NOT supported.

· Can be used as BOOT NVM *

Note – The SDIO signals are multiplexed with other functional options. Refer to the Pin MUX tools for optional functionalities.

MCAN

The AM64xx supports up to two CAN interfaces.

MCAN main features are:

· Conforms with CAN Protocol 2.0 A, B and ISO 11898-1:2015.

· Full CAN FD support (up to 64 data bytes).

Note – The MCAN signals are multiplexed with other functional options. Refer to the Pin MUX tools for optional functionalities.

ADC

The AM64xx support up to eight Analog to Digital lines. The Analog-to-Digital Converter (ADC) module contains a single 12-bit ADC which can be multiplexed to any 1of 8 analog inputs (channels).

· 4 MSPS rate with a 60 MHz SMPL_CLK.

· Functional Internal Diagnostic Debug Mode.

· Single-ended or differential input options.

· Simultaneous sampling is NOT supported.

GPIO

The AM64xx support GPIO interfaces that can be multiplex with alternative function interfaces. Some of the interfaces are:

· Fast serial interface (FSI).

· Enhanced Capture Module.

· Enhanced PWM.

· Timers

· More

Refer to the Pin MUX tools for optional functionalities.

Connector’s Signal Description

J5001

Pin Number	Signal Name (SoM v1.1 schematics)	SoC Ball Name	SoC Ball Number	IO Voltage	Function on HummingBoard-T Carrier	Signal Name (HummingBoard-T v1.2 Schematics)
1	BOOTMODE0 (GPIO0_15)	GPMC0_AD0	T20	3V3		NC
2	BOOTMODE13//FSI_RX1_D1 (GPIO0_28)	GPMC0_AD13	V18	3V3	PU/PD (R88/R99)	BOOTMODE13//FSI_RX1_D1
3	BOOTMODE3 (GPIO0_18)	GPMC0_AD3	U20	3V3	DIP-Switch (S1-12, PD)	BOOTMODE3
4	BOOTMODE12//FSI_RX1_D0 (GPIO0_27)	GPMC0_AD12	W21	3V3	PU/PD (R89/R100)	BOOTMODE12//FSI_RX1_D0
5	BOOTMODE1 (GPIO0_16)	GPMC0_AD1	U21	3V3		NC
6	BOOTMODE11/FSI_RX1_CLK (GPIO0_26)	GPMC0_AD11	W20	3V3	PU/PD (R90/R101)	BOOTMODE11/FSI_RX1_CLK
7	PRG0_MDIO0_MDIO (GPIO1_40)	PRG0_MDIO0_MDIO	P2	3V3	SerDes MUX Select (M1 or M2)	PCIe_SEL
8	WLAN_IRQ GPIO0_12	OSPI0_CSN1	L18	1V8	M.2 Reset (M2-67)	M.2_RESET#
9	BOOTMODE5 (GPIO0_83)	GPMC0_AD5	U19	3V3	DIP-Switch (S1-10, PD) / EXTENDER (J5-4)	BOOTMODE5
10	GPMC0_DIR (GPIO0_40)	GPMC0_DIR	N17	3V3	Battery Charger Processor Hot (U3-11)	PROCHOTn
11	BOOTMODE4 (GPIO0_82)	GPMC0_AD4	U18	3V3	DIP-Switch (S1-11, PD)	BOOTMODE4
12	BOOTMODE9/FSI_RX0_D0 (GPIO0_24)	GPMC0_AD9	T17	3V3	DIP-Switch (S1-7, PD)	BOOTMODE9/FSI_RX0_D0
13	GND					GND
14	BOOTMODE8/FSI_RX0_CLK (GPIO0_23)	GPMC0_AD8	V19	3V3	DIP-Switch (S1-8, PD)	BOOTMODE8/FSI_RX0_CLK
15	BOOTMODE7 (GPIO0_22)	GPMC0_AD7	V21	3V3	PU/PD (R87/R98)	BOOTMODE7
16	GND					GND
17	BOOTMODE6 (GPIO0_21)	GPMC0_AD6	V20	3V3	DIP-Switch (S1-9, PD) / EXTENDER (J5-5)	BOOTMODE6
18	GPMC0_ADVn_ALE (GPIO0_32)	GPMC0_ADVN_ALE	P16	3V3	M.2 WiFi Disable (M2-8)	M.2_W_DIS#
19	PRG0_MDIO0_MDC (GPIO1_41)	PRG0_MDIO0_MDC	P3	3V3	SerDes MUX Enable	PCIe_EN
20	PRG0_PRU0GPO5/UART3_RTSn	PRG0_PRU0_GPO5	R3	3V3	RS-485-RE#/DE (U18-2/3)	PRG0_PRU0GPO5/UART3_RTSn
21	BOOTMODE2 (GPIO0_17)	GPMC0_AD2	T18	3V3		NC
22	GND					GND
23	WL_RTC_CLK (GPIO0_34)	GPCM0_WEN	T21	3V3	M.2 Bluetooth / GPS Disable (M2-26)	M.2_GPS_BT_EN#
24	PRG0_PRU1GPO6	PRG0_PRU1_GPO6	R5	3V3	EXTENDER (J5-17)	PRG0_PRU1GPO6
25	PRG0_PRU1GPO5	PRG0_PRU1_GPO5	R4	3V3	EXTENDER (J5-15)	PRG0_PRU1GPO5
26	PRG0_PRU0GPO15	PRG0_PRU0_GPO15	T5	3V3	M.2 PCI Reset (M2-50, M1-52)	PERST#
27	PRG0_PRU0GPO1	PRG0_PRU0_GPO1	R4	3V3	EXTENDER (J5-33)	PRG0_PRU0GPO1
28	PRG0_PRU1GPO13	PRG0_PRU1_GPO13	T6	3V3	EXTENDER (J5-21)	PRG0_PRU1GPO13
29	PRG0_PRU0GPO13	PRG0_PRU0_GPO13	R6	3V3	EXTENDER (J5-7)	PRG0_PRU0GPO13
30	PRG0_PRU1GPO14	PRG0_PRU1_GPO14	U6	3V3	EXTENDER (J5-14)	PRG0_PRU1GPO14
31	PRG1_IEP0_EDC_SYNC_OUT2	PRG1_PRU0_GPO17	U7	3V3		NC
32	PRG0_PRU1GPO15	PRG0_PRU1_GPO15	U5	3V3	M.2 PCI Clock Request (M2-52)	CLKREQ1#
33	GND			3V3		GND
34	BT_EN GPIO1_78	MMC1_SDWP	C20	3V3	SoC Programming power enable	VPP_LDO_EN
35	PRG0_PRU1GPO3	PRG0_PRU1_GPO3	T4	3V3	EXTENDER (J5-12)	PRG0_PRU1GPO3
36	GND					GND
37	PRG0_PRU0GPO16	PRG0_PRU0_GPO16	U4	3V3		NC
38	NC					NC
39	PRG0_PRU0GPO19/UART3_RXD	PRG0_PRU0_GPO19	W1	3V3	RS-485-R (U18-1)	PRG0_PRU0GPO19/UART3_RXD
40	PRG0_PRU1GPO2	PRG0_PRU1_GPO2	V3	3V3	EXTENDER (J5-31)	PRG0_PRU1GPO2
41	GPMC0_WAIT0 (GPIO0_37)	GPMC0_WAIT0	W19	3V3	Tamper Detection External Interrupt (J15-1)	TAMPER
42	PRG0_PRU0GPO6	PRG0_PRU0_GPO6	T3	3V3	EXTENDER (J5-26)	PRG0_PRU0GPO6
43	PRG0_PRU0GPO0	PRG0_PRU0_GPO0	Y1	3V3	EXTENDER (J5-32)	PRG0_PRU0GPO0
44	PRG0_PRU1GPO1	PRG0_PRU1_GPO1	W2	3V3	EXTENDER (J5-22)	PRG0_PRU1GPO1
45	PRG0_PRU1GPO0	PRG0_PRU1_GPO0	Y2	3V3	EXTENDER (J5-23)	PRG0_PRU1GPO0
46	PRG0_PRU0GPO3/UART3_CTSn	PRG0_PRU0_GPO3	V2	3V3	RS-485-RE#/DE (U18-2/3)	PRG0_PRU0GPO3/UART3_CTSn
47	GND					GND
48	PRG0_PRU0GPO2	PRG0_PRU0_GPO2	U2	3V3		NC
49	PRG0_PRU1GPO16	PRG0_PRU1_GPO16	AA4	3V3		NC
50	PRG0_PRU0GPO11	PRG0_PRU0_GPO11	Y3	3V3	M.2 PCI Clock Request (M1-53)	CLKREQ2#
51	PRG0_PRU0GPO12	PRG0_PRU0_GPO12	AA3	3V3	EXTENDER (J5-6)	PRG0_PRU0GPO12
52	GND					GND
53	PRG0_PRU0GPO8	PRG0_PRU0_GPO8	T2	3V3		NC
54	PRG0_PRU0GPO4/UART3_TXD	PRG0_PRU0_GPO4	AA2	3V3	RS-485-D (U18-4)	PRG0_PRU0GPO4/UART3_TXD
55	PRG0_PRU0GPO7	PRG0_PRU0_GPO7	T1	3V3	EXTENDER (J5-16)	PRG0_PRU0GPO8
56	PRG0_PRU0GPO18	PRG0_PRU0_GPO18	V1	3V3		NC
57	GND					GND
58	PRG0_PRU1GPO12	PRG0_PRU1_GPO12	Y4	3V3	EXTENDER (J5-18)	PRG0_PRU1GPO12
59	PRG0_PRU1GPO8	PRG0_PRU1_GPO8	R1	3V3	EXTENDER (J5-20)	PRG0_PRU1GPO8
60	PRG0_PRU0GPO17	PRG0_PRU0_GPO17	U18	3V3	PCIe_3V3_EN (M.2 PWR_EN)	PCIe_3V3_EN
61	PRG0_PRU1GPO4	PRG0_PRU1_GPO4	W3	3V3	EXTENDER (J5-13)	PRG0_PRU1GPO4
62	PRG0_PRU1GPO11	PRG0_PRU1_GPO11	W4	3V3	EXTENDER (J5-19)	PRG0_PRU1_GPO11
63	GND					GND
64	GND					GND
65	PRG0_PRU0GPO14	PRG0_PRU0_GPO14	V4	3V3		NC
66	SoC_WARM_RESETZ	RESET_REQZ	E18	3V3		NC
67	PRG1_IEP0_EDC_LATCH_IN0	PRG1_PRU0_GPO18	V7	3V3		NC
68	NC					NC
69	PRG1_IEP0_EDC_SYNC_OUT0	PRG1_PRU0_GPO19	W7	3V3		NC
70	NC					NC

J7

Pin Number	Signal Name (SoM schematics)	SoC Ball Name	SoC Ball Number	IO Voltage	Function on HummingBoard-T Carrier	Signal Name (HummingBoard-T v1.2 Schematics)
1	GPMC0_BE1n/I2C2_SDA (GPIO0_44)	GPMC0_CSN3	R21	3V3	Real-Time Clock Interrupt	RTC_INT#
2	GPMC0_BE1n/FSI_TX0_CLK (GPIO0_37)	GPMC0_BE1N	T19	3V3		NC
3	GPMC0_WAIT1/FSI_TX1_D1 (GPIO0_38)