RZ/G2L and RZ/V2L SOM Hardware User Manual
Revisions and Notes
Date
Owner
Revision
Notes
11 Oct 2023
Mikhail Anikin
1.0
16 Oct 2023
Sasha Strizhiver
1.1
general comments
Nov 2, 2023
Shahar Fridman
1.2
Add Power Consumption Measurement
31 Dec 2024
Yazan Shhady
1.3
Add SOM Rev 1.2 changes: 1. Connect the WIFI clock (PMIC_32KHz_CLK) to Pull Up 2. Move RZ_P5_1 from J7-33 to J7-13 to support M.2 Reset on the HBP 3. Move RZ_P5_0 from J7-39 to J7-15 4. Move RZ_P5_2 from J7-37 to J7-8 5. Enable power control from BtB. Adding U14 (PU/PD select) 6. Move RZ_P16_0 from J7-59 to J7-79 7. Add AUDIO_CLK to J7-59 8. Add R116 to support RTC clock from MPIO2. 9. Swapping I2C1 pins on J9: SOM V1.2=> J9-51-SDA, J9-53-SCL (SOM V1.1 => J9-51-SCL, J9-53-SDA).
Introduction
This User Manual relates to the SolidRun’s RZG2 series, which includes
RZG2L Dual-core ARM A55 (1.2GHz) w Cortex-M33 (200MHz)
RZV2L Dual-core ARM A55 (1.2GHz) w Cortex-M33 (200MHz) and Renesas Original AI Accelerator "DRP-AI"
Overview
The SolidRun’s RZG2L/V2L family is a high-performance 64-Bit Renesas. RZ/G2 Based SOMs with Integrated GPU for Next-Gen Human-Machine Interfaces. RZV2L is adding an AI accelerator to the G2L.
Ideal for automation, smart buildings, network cameras, and IoT devices, SolidRun RZ/G2 SOMs combine a powerful MPU, GPU, extended ECC, Ethernet, and offer long-term Linux software support.
Highlighted Features
Ultra-small footprint SOM (47x30mm) including three board-to-board connectors (250 total pins number).
Renesas’s SoC supports the DUAL version.
Dual Cortex A55 and up to 1.2GHz
Cortex-M33 subsystem processor supports real-time tasks.
Video codec (H.264).
AI accelerator; DRP-AI (V2L only)
High-security engines.
Dual Ethernet interfaces.
Up to two CAN interfaces.
High industrial reliability with in-line ECC on DDR4 and on on-chip RAM.
Single MIPI-CSI and single MIPI-DSI (H.264)
Optional RGB interface.
Two USB 2.0.
DDR4 memory in x16 configurations supports up to 2GB and up to 1.6GT/s.
Up to 128GB eMMC.
1Mb QSPI NOR Flash
Wi-Fi 11b/g/n/ac + Bluetooth 5.0 certified module
1Mb QSPI NOR Flash
1Kb I2C EEPROM
Power management devices
Commercial and industrial temperature grade support.
Supporting Products
The following products are provided by SolidRun both as production-level platforms and as reference examples on how to incorporate the SOM in different levels of integration:
HummingBoard Pro – An extended board computer incorporating the SOM with different Linux distributions while adding extra hardware functionalities and access to the hardware.
Description
Block Diagram
The following figure describes the RZ/G2L Blocks Diagram.
Features Summary
Following are the features summary of the SOM. Notice that some of the features are pinout multiplexed (please refer to the pin mux table below and the Renesas datasheets):
Renesas’s RZG2 series SoC (Dual ARM® Cortex™ A55 Processor, up to 1.2 GHz)
Cortex-M33 (200MHz) subsystem processor.
AI accelerator; DRP-AI (V2L only)
Up to 2GByte DDR4 memory and up to 1.6GT/s
Eight bits eMMC 5.1 memory or a four bits SD interface
1Kb I2C EEPROM.
8Mb QSPI NOR Flash.
4-lanes MIPI-DSI interface
Optional RGB (8,8,8) interface.
3D graphics engine (Arm Mali-G31).
Video codec (H.264).
4-lanes MIPI CSI-2
Dual 10/100/1000 Mbps Ethernet PHY
Wi-Fi (802.11a/b/g/n/ac) + BT (5.0) Murata's certified module
Two USB 2.0 Host and Device
Single eSPI interface.
Up to four Serial interfaces.
Up to 2 CAN-FD.
Power:
A single 5.0V input using B-to-B connector.
3.3V/1A output to support carrier's digital interfaces.
RAA215300 PMIC
Core System Components
RZ/G2L SoC Family
Ideal for automation, smart buildings, network cameras, and IoT devices, SolidRun RZ/G2 SOMs combine a powerful MPU, GPU, extended ECC, Ethernet, and offer long-term Linux software support
A verified Linux Package (VLP) reduces cost and simplifies design.
MEMORIES
The RZG2L SOM supports a variety of memory interfaces for booting and data storage. The following figure describes the RZG2L memory interfaces.
DDR4
Up to 2GB memory space.
16 Bits data bus.
Up to 1600 MT/s.
ECC function for single-bit and double-bit error reporting, single-bit error correction, and programmable removal of ECC storage
Support various low-power modes, clocks, and power-gated operations.
Support Self-Refresh mode.
eMMC and SD NAND Memory
SD0 of the RZG2L/V2L can be configured as an 8-bit eMMC interface or a 4-bit SDIO. Configuration can be done during the boot process (Boot strap pins, SD0_DEV_SEL) or by SW (SD0_DEV_SEL_SW, GPIO_P22_1).
Selecting SD0’s physical connection (eMMC or uSD card) is done by an analog switch.
The state of the analog switch can be set by a DIP-Switch, SW or PU/PD resistors.
eMMC
Up to 128GB memory space.
8 Bits data bus.
Support MMC standard, up to version 4.5.1.
Supports High-speed, HS200 transfer modes
uSDHC-0.
Can be used as BOOT NVM **
Micro-SD (Carrier)
Optional on the carrier board
uSDHC-0.
Implements 4 data bits.
Support SD/SDIO standard up to version 3.0.
SD, SDHC, and SDXC SD memory card access supported.
Default, high-speed, UHS-I/SDR50, and SDR104 transfer modes supported
Can be used as BOOT NVM **
Quad Serial NOR Flash (SOM)
Each channel can be configured as a 1/2/4-bit operation.
Support both SDR (66MHz) mode and DDR (50MHz) mode
No reset
QSPIA/nSS0.
Can be used as BOOT NVM **
EEPROM (SOM)
1Kb EEPROM
ON-Semi’s CAT24AA01TDI or compatible
I2C0
Address 0X50 (7 bits format)
Stores SOM’s configurations.
Serial NOR Flash (Carrier)
Optional on carrier board
1-bit data bus.
eSPI1/nSS0
Can be used as BOOT NVM *
* Note – eMMC and uSD share the same signals. ** Note – Boot configuration is set by the Boot-strap pins
10/100/1000 Mbps Ethernet PHY
The SOM supports two fast Ethernet interfaces.
RGMII interface.
802.3 Ethernet interface for 1000BASE-T, 100BASE-TX, and 10BASE-T.
MaxLinear's MxL86110I PHY.
Auto-MDIX and polarity correction.
Energy-Efficient Ethernet (EEE) and power down mode.
10k byte jumbo frame support.
WI-FI (802.11AC/A/B/G/N) AND BT 5.3 (MURATA'S CERTIFIED MODULE)
WI-FI & BT
The WI-FI & BT module is Murata’s 1MW module Based on Cypress CYW43455 chip. The WI-FI main features are:
Operate at ISM frequency Band (2.4/5 GHz)
IEEE Standards Support 802.11a, 802.11b, 802.11g, 802.11n, 802.11ac
WI-FI over SDIO-1 interface
BT 5.3 BR/EDR/LE
BT over UART-2 Interface
Global certification.
External Interfaces
General
The SOM incorporates three Hirose DF40 board-to-board headers.
The selection of the Hirose DF40 is due to the following criteria:
Miniature (0.4m pitch)
Highly reliable manufacturer
Availability (worldwide distribution channels)
Excellent signal integrity (supports 6Gbps)
Please contact Hirose or SolidRun for reliability and test result data.
Mating height of between 1.5mm to 4.0mm (1.5mm to 3.0mm if using 70-pin Board-to-Board header). RZG2L/V2L SOM’s headers are fixed, the final mating height is determined by carrier implementation
USB 2.0
The RZG2L/V2L supports two USB 2.0 interfaces. The following figure describes the USB interfaces.
The USB’s main features are:
Single USB 2.0 OTG/DRD(Host/Function) interface (USB0)
Single USB 2.0 Host interface (USB1).
Support mode: High-Speed(480Mbps)/Full-Speed(12Mbps)/Low-Speed(1.5Mbps).
OTG function (Rev2.0).
B2B Connector’s Signal Description
DRD (Dual-Role-Device) function (Static switch between Host and Function).
Power control signals are not part of the USB module, any available GPIO can be used.
Note – The voltage on VBUS is 5V.
MIPI CSI
The following figure describes the CSI interface.
Supports MIPI CSI-2 V2.1 and MIPI D-PHY V2.1 (80 Mbps ~ 1500 Mbps).
Maximum image size: 5 M pixels.
Minimum image size: QVGA (320 × 240) ＝ 76.8 K pixels.
Maximum number of valid pixels in the horizontal direction: 2800 pixels.
Maximum number of valid pixels in the vertical direction: 4095 lines
Support 1/2/4 lanes.
Support 4 Virtual Channel.
MIPI DSI
The following figure describes the DSI interface.
The DSI main features are:
Display Serial Interface Version 1.3.1.
Support up to Full HD (1920 × 1080), 60 fps (RGB888).
Maximum Bandwidth: 1.5 Gbps per lane, 4 data lanes.
Support Output Data Format: RGB666 / RGB888.
Supports 1, 2, 3 and 4 lane configurations.
Support for Virtual Channel
Parallel Interface
Support WXGA (1280x800), 60 fps.
Support Output Data Format: RGB666 / RGB888.
CLK / HD / VD timing signal supported.
UART
Up to 4 UART interfaces. The following figure describes the UART interfaces.
The UART interface's main features are:
UART 2 is connected directly to the WI-FI/BT Modem to support the BT. It is NOT available on the SOM B-t-B connector.
UART 0 supports TX, RX and is used as terminal interface
UART 1 supports TX, RX, CTS and RTS.
UART 3 supports TX and RX.
UART 3 supports TX and RX.
Selectable bit rate with an on-chip baud rate generator.
Note – UART interfaces are available as ALT functional signals of other signals.
SPI
Up to 3 SPI interfaces. The following figure describes the eSPI interface.
Single chip select nSS0.
Master/Slave configurable.
Switching of the polarity of the serial transfer clock.
Switching of the clock phase of serial transfer.
Transfer bit-length is selectable as 8, 16, or 32 bits.
Note SPI interfaces are available as ALT functional signals of other signals.
I2C
Up to 4 I2C Interfaces. The following figure describes the I2C interfaces.
The I2C main features are:
I2C-3 is used only on the SOM. It is connected to the PMIC.
I2C-0 is available on the connector and connected to the SOM’s EEPROM.
I2C-1 and I2C2 are available on the BtB connectors.
I2C bus format or SMBus format.
Master mode or slave mode selectable
Up to 1 Mbps.
Up to three slave-address settings can be made.
Internal time-out function is capable of detecting long-interval stop of the SCL (clock signal).
Note – I2C interfaces are available as ALT functional signals of other signals.
uSD
The uSD interface is multiplexed with the eMMC interface. Only one of them is available.
CAN-FD
Up to 2 CANFD interfaces are available. The following figure describes the CAN interfaces.
The CAN main features are:
Supports two interface modes, classical CAN mode and CANFD mode.
ISO11898-1 compliant.
Maximum 1 Mbps in classical CAN mode.
Nominal bit rate: max.1 Mbps, data bit rate: max. 4 Mbps in CANFD mode.
CONNECTOR’S SIGNAL DESCRIPTION
J5001
PIN
HBP 2.5
RZG2L 1.2
PIN
HBP 2.5
RZG2L 1.2
1
TP4
NC
2
NC
NC
3
DIP-SWITCH
1V8
MD0
1V8
4
DSI-CON (J19) or DSI-HDMI
RZ_DSI_DATA3_N
5
DIP-SWITCH
1V
MD1
1V8
6
DSI-CON (J19) or DSI-HDMI
RZ_DSI_DATA3_P
7
GND
GND
8
GND
GND
9
DSI-CON (J19) or DSI-HDMI
RZ_DSI_CLK_P
10
GND
GND
11
DSI-CON (J19) or DSI-HDMI
RZ_DSI_CLK_N
12
DSI-CON (J19) or DSI-HDMI
RZ_DSI_DATA0_N
13
GND
GND
14
DSI-CON (J19) or DSI-HDMI
RZ_DSI_DATA0_P
15
DSI-CON (J19) or DSI-HDMI
RZ_DSI_DATA2_N
16
GND
GND
17
DSI-CON (J19) or DSI-HDMI
RZ_DSI_DATA2_P
18
Mini-PCIe (J20, optional)
NC
19
GND
GND
20
Mini-PCIe (J20, optional)
NC
21
DSI-CON (J19) or DSI-HDMI
RZ_DSI_DATA1_N
22
GND
GND
23
DSI-CON (J19) or DSI-HDMI
RZ_DSI_DATA1_P
24
M.2_W_DIS#
1V8
DISP_DATA15/GPIO_P14_0
3V3
25
GND
GND
26
Mini-PCIe_W_DIS#
3V3
DISP_DATA16/GPIO_P14_1
3V3
27
M.2_WAKW_ON_LAN (PCIe)
NA
GPIO_P19_1
3V3
28
USB1_PWR_EN
3V3
RZ_USB0_VBUSEN
3V3
29
MIKROBUS (J10-4)
NA
RZ_SCIF1_TXD
3V3
30
GND
GND
31
MIKROBUS (J10-3)
NA
RZ_SCIF1_RXD
3V3
32
Mini-PCIe (J20, optional)
NC
33
GND
GND
34
Mini-PCIe (J20, optional)
NC
35
NC
GPIO_P19_0
3V3
36
GND
GND
37
MIKROBUS (J10-1)
NA
RZ_SCIF1_CTS
3V3
38
Mini-PCIe (J20, optional)
NC
39
MIKROBUS (J10-2)
NA
RZ_SCIF1_RTS
3V3
40
Mini-PCIe (J20, optional)
NC
41
HEADER, DIP-SW
3V3
MD2
1V8
42
GND
GND
43
DSI_TS_nINT (DSI-HDMI)
3V3
DISP_DATA5/GPIO_P9_1
3V3
44
LED (D34)
3V3
DISP_DATA0/GPIO_P7_2
3V3
45
NC
DISP_DATA6/GPIO_P10_0
3V3
46
LED (D33)
3V3
GPIO_P48_2
3V3
47
GND
GND
48
LED (D32)
3V3
GPIO_P47_1
3V3
49
NC
GPIO_P40_2
3V3
50
LED (D31)
3V3
GPIO_P47_2
3V3
51
HEADER, DIP-SW
3V3
GPIO_P47_3
3V3
52
GND
GND
53
WIFI_DP (HUB to IMX8M)
NA
ADC_CH0
54
CSI-CON(CON7)
RZ_CSI_DATA0_N
55
WIFI_DN (HUB to IMX8M)
NA
ADC_CH3
56
CSI-CON(CON7)
RZ_CSI_DATA0_P
57
GND
GND
58
GND
GND
59
CSI-CON(CON7)
RZ_CSI_CLK_P
60
CSI-CON(CON7)
RZ_CSI_DATA2_P
61
CSI-CON(CON7)
RZ_CSI_CLK_N
62
CSI-CON(CON7)
RZ_CSI_DATA2_N
63
GND
GND
64
GND
GND
65
CSI-CON(CON7)
RZ_CSI_DATA3_P
66
CSI-CON(CON7)
RZ_CSI_DATA1_P
67
CSI-CON(CON7)
RZ_CSI_DATA3_N
68
CSI-CON(CON7)
RZ_CSI_DATA1_N
69
GND
GND
70
GND
GND
J7
PIN
HBP 2.5
RZG2L 1.2
PIN
HBP 2.5
RZG2L 1.2
1
ETH_NIC (Intel, U6)
NC
2
ETH_NIC (Intel, U6)
NC
3
ETH_NIC (Intel, U6)
NC
4
ETH_NIC (Intel, U6)
NC
5
GND
GND
6
GND
GND
7
ETH_NIC (Intel, U6)
NC
8
HEADER (CON4)
NA
GPIO_P5_2 (was NC in SOM Rev 1.1)
9
ETH_NIC (Intel, U6)
NC
10
mPCIe (J20)
3V3
GPIO_P42_2
3V3
11
GND
GND
12
HEADER (CON4)
NA
GPIO_P42_3
3V3
13
M.2_RESET#
1V8
GPIO_P5_1 (was NC in SOM Rev 1.1)
14
POE_AT_DET
3V3
DISP_DATA17/GPIO_P15_0
3V3
15
RTC_CLKO (RTC Int.)
3V3
GPIO_P5_0 (was NC in SOM Rev 1.1)
16
DSI-CON (J19) or DSI-HDMI
NA
DISP_DATA18/GPIO_P15_1
3V3
17
GND
GND
18
M.2_PCIe_3V3_EN
3V3
DISP_DATA21/GPIO_P17_0
3V3
19
HDMI CON (J1)
NC
20
HEADER (CON4)
NA
DISP_DATA22/GPIO_P17_1
3V3
21
HDMI CON (J1)
NC
22
HEADER (CON4)
NA
DISP_DATA23/GPIO_P17_2
3V3
23
GND
GND
24
HEADER (CON4)
NA
DISP_CLK/GPIO_P6_0
3V3
25
HDMI CON (J1)
NC
26
USB-HUB_RST#
3V3
GPIO_P39_1
3V3
27
HDMI CON (J1)
NC
28
HEADER (CON4)
NA
GPIO_P39_2
3V3
29
GND
GND
30
HEADER (CON4)
NA
DISP_HSYNC/GPIO_P6_1
3V3
31
HDMI CON (J1)
NC
32
TP6
DISP_VSYNC/GPIO_P7_0
3V3
33
HDMI CON (J1)
NC (was GPIO_P5_1 in SOM Rev 1.1)
3V3
34
NC
DISP_DE/GPIO_P7_1
3V3
35
GND
GND
36
HEADER (CON4)
NA
GPIO_P36_1
3V3
37
HDMI CON (J1)
NC (was GPIO_P5_2 in SOM Rev 1.1)
3V3
38
CSI-CON(CON7)
NA
RZ_SCIF3_TXD
3V3
39
HDMI CON (J1)
NC (was GPIO_P5_0 in SOM Rev 1.1)
3V3
40
NC
GPIO_P32_1
3V3
41
GND
GND
42
GND
GND
43
HDMI CON (J1)
3V3
DISP_DATA9/GPIO_P11_1
3V3
44
LED (D30)
3V3
RZ_SCIF3_RXD
3V3
45
HDMI CON (J1)
5V
DISP_DATA10/GPIO_P12_0
3V3
46
HEADER (CON4)
NA
GPIO_P33_0
3V3
47
HDMI CON (J1)
5V
DISP_DATA13/GPIO_P13_1
3V3
48
GND
GND
49
HDMI CON (J1)
5V
DISP_DATA14/GPIO_P13_2
3V3
50
HEADER (CON4)
NA
GPIO_P32_0
3V3
51
AUDIO CODEC
3V3
RZ_SSI0_BCK
3V3
52
TERMINAL_TX
3V3
RZ_SCIF0_TXD
3V3
53
AUDIO CODEC
3V3
RZ_SSI0_TXD
3V3
54
TERMINAL_RX
3V3
RZ_SCIF0_RXD
3V3
55
AUDIO CODEC
3V3
RZ_SSI0_RCK
3V3
56
NC
DISP_DATA20/GPIO_P16_1
3V3
57
AUDIO CODEC
3V3
RZ_SSI0_RXD
3V3
58
GND
GND
59
AUDIO CODEC
3V3
AUDIO_CLK (was GPIO_P16_0/DISP_DATA19 in SOM Rev 1.1)
3V3
60
USB-HUB
NC
61
GND
GND
62
USB-HUB
NC
63
HEADER (CON4)
NA
VDD_RTC
3V3
64
GND
GND
65
RESET-B
1V8
SYS_nRST
1V8
66
USB-HUB
NC
67
HEADER (CON4)
NA
ETH1_TRX3_P
68
USB-HUB
NC
69
HEADER (CON4)
NA
ETH1_TRX3_N
70
GND
GND
71
HEADER (CON4)
NA
ETH1_TRX2_P
72
HEADER (CON4)
NA
ETH1_TRX1_P
73
MICRO-SD
NA
ETH1_TRX2_N
74
HEADER (CON4)
NA
ETH1_TRX1_N
75
GND
GND
76
GND
GND
77
HDMI CON (J1)
NC
78
HEADER (CON4)
NA
ETH1_TRX0_P
79
HDMI CON (J1)
GPIO_P16_0/DISP_DATA19 (was NC in SOM Rev 1.1)
80
HEADER (CON4)
NA
ETH1_TRX0_N
J9
PIN
HBP 2.5
RZG2L 1.2
PIN
HBP 2.5
RZG2L 1.2
1
ETH-POE
ETH_TRX3_N
2
GND
GND
3
ETH-POE
ETH_TRX3_P
4
USB-TYPE-A
GPIO_P1_0
3V3
5
GND
GND
6
USB-TYPE-A
GPIO_P43_0
3V3
7
ETH-POE
ETH_TRX2_N
8
GND
GND
9
ETH-POE
ETH_TRX2_P
10
USB-TYPE-A
NC
11
GND
GND
12
USB-TYPE-A
RZ_USB1_OVERCUR
3V3
13
ETH-POE
ETH_TRX1_N
14
GND
GND
15
ETH-POE
ETH_TRX1_P
16
USB-TYPE-A
RZ_USB0_DP
17
GND
GND
18
USB-TYPE-A
RZ_USB0_DM
19
ETH-POE
ETH_TRX0_N
20
GND
GND
21
ETH-POE
ETH_TRX0_P
22
USB-HUB
RZ_USB1_DP
23
GND
GND
24
USB-HUB
RZ_USB1_DM
25
ETH-LED
LED_0/PHY_CFG0
3V3
26
GND
GND
27
ETH-LED
LED1_0/PHY_CFG1
3V3
28
M.2_GPS_EN#
NA
RZ_SCIF4_RX
3V3
29
HEADER (CON4)
GPIO_P43_1
3V3
30
J9-59 (BT_FW_FLASH, J9-59)
NA
RZ_SCIF4_TX
3V3
31
MIPI-DSI, ETH-NIC, DSI-CON, CSI-CON, RTC, MIKROBUS
3V3
RZ_RIIC0_SCL
3V3
32
MIKROBUS (J8-3)
NA
RZ_RSPI1_SSL
3V3
33
MIPI-DSI, ETH-NIC, DSI-CON, CSI-CON, RTC, MIKROBUS
3V3
RZ_RIIC0_SDA
3V3
34
CSI-CON (J19) or DSI-HDMI
3V3
RZ_SCIF4_CLK
3V3
35
GND
GND
36
GND
GND
37
USB_HUB_CH1_PWR_EN
3V3
RZ_USB1_VBUSEN
3V3
38
MICRO-SD
SD2
SD_SD0_CLK
SD2
39
J9-55 (BT_FW_FLASH, J9-55)
NA
GPIO_P43_2
3V3
40
MICRO-SD
SD2
SD_SD0_CMD
SD2
41
ETH-NIC RST# (Intel, U6)
3V3
GPIO_P43_3
3V3
42
MICRO-SD
SD2
SD_SD0_DATA0
SD2
43
USB1_VBUS
5V
RZ_USB0_VBUSIN
5V
44
MICRO-SD
SD2
SD_SD0_DATA1
SD2
45
MIKROBUS (J8-5)
NA
RZ_RSPI1_MISO
3V3
46
MICRO-SD
SD2
SD_SD0_DATA2
SD2
47
MIKROBUS (J8-6)
NA
RZ_RSPI1_MOSI
3V3
48
MICRO-SD
SD2
SD_SD0_DATA3
SD2
49
MIKROBUS (J8-4)
NA
RZ_RSPI1_CK
3V3
50
MICRO-SD
SD2
RZ_SD0_CD
SD2
51
AUD_CODEC, USB-TYPEC, USB-HUB
3V3
RZ_RIIC1_SDA (Was RZ_RIIC1_SCL in SOM Rev 1.1)
3V3
52
USB-HUB
3V3
RZ_RSPI2_CK
3V3
53
AUD_CODEC, USB-TYPEC, USB-HUB
3V3
RZ_RIIC1_SCL (Was RZ_RIIC1_SDA in SOM Rev 1.1)
3V3
54
HEADER, DIP-SW
3V3
RZ_RSPI2_MOSI
3V3
55
BT-FW_FLASH (J9-39)
NA
DISP_DATA8/RZ_CAN0_RX
56
NC
RZ_RSPI2_MISO
3V3
57
HEADER (CON4)
NA
DISP_DATA7/RZ_CAN0_TX
58
NC
RZ_RSPI2_SSL
3V3
59
BT-FW_FLASH (J9-30)
NA
DISP_DATA12/RZ_CAN1_RX
60
NC
RZ_WDTOVF_PERROUT
3V3
61
MICRO-SD
DISP_DATA11/RZ_CAN1_TX
62
PUSH-B
PMIC_PWRON
3V3
63
3V3_IN
3V3_OUT
64
HEADER, DIP-SW
3V3
SD0_DEV_SEL
3V3
65
3V3_IN
3V3_OUT
66
NC
PMIC_EN
3V3
67
3V3_IN
3V3_OUT
68
MICRO-SD
NA
GPIO_SD0_PWR_EN
3V3
69
3V3_IN
3V3_OUT
70
GND
GND
71
VIN_5V0
VIN_5V0
72
GND
GND
73
VIN_5V0
VIN_5V0
74
GND
GND
75
VIN_5V0
VIN_5V0
76
GND
GND
77
VIN_5V0
VIN_5V0
78
GND
GND
79
VIN_5V0
VIN_5V0
80
GND
GND
mikroBUS
HBP 2.4
RZG2L 1.1
MIKROBUS (J8-2)
RZ_SSI0_RXD
MIKROBUS (J8-3)
RZ_RSPI1_SSL
MIKROBUS (J8-4)
RZ_RSPI1_CK
MIKROBUS (J8-5)
RZ_RSPI1_MISO
MIKROBUS (J8-6)
RZ_RSPI1_MOSI
MIKROBUS (J10-1)
RZ_SCIF1_CTS
MIKROBUS (J10-2)
RZ_SCIF1_RTS
MIKROBUS (J10-3)
RZ_SCIF1_RXD
MIKROBUS (J10-4)
RZ_SCIF1_TXD
MIKROBUS (J10-5)
RZ_RIIC0_SCL
MIKROBUS (J10-6)
RZ_RIIC0_SDA
LCD (Parallel Video Output) Signals allocation
LCD
B-to-B connector
DISP_DATA0
J5001-44
DISP_DATA1
J9-52
DISP_DATA2
J9-54
DISP_DATA3
J9-56
DISP_DATA4
J9-58
DISP_DATA5
J5001-43
DISP_DATA6
J5001-45
DISP_DATA7
J9-57
DISP_DATA8
J9-55
DISP_DATA9
J7-43
DISP_DATA10
J7-45
DISP_DATA11
J9-61
DISP_DATA12
J9-59
DISP_DATA13
J7-47
DISP_DATA14
J7-49
DISP_DATA15
J5001-24
DISP_DATA16
J5001-26
DISP_DATA17
J7-14
DISP_DATA18
J7-16
DISP_DATA19
J7-79 (Was J7-59 in SOM Rev 1.1)
DISP_DATA20
J7-56
DISP_DATA21
J7-18
DISP_DATA22
J7-20
DISP_DATA23
J7-22
DISP_HSYNC
J7-30
DISP_VSYNC
J7-32
DISP_DE
J7-34
DISP_CLK
J7-24
Power & Reset
The RZG2L/V2L SOM power source is a single 5V source. It uses Renesas’s PMIC to source all the SOM's power rails. The following figure describes the power architecture.
The power architecture's main features are:
Single 5V power source.
Renesas’s RAA215300 sources the RZG2L/V2L power rails.
3.3V output up to 0.6A (Need to calculate system and SOM power).
Power up sequence is supported by the PMIC configuration.
POWER CONSUMPTION
RZ/G2L Power Table
Mode
Voltage
Current
Power
Idle, Linux up
5V
240mA
1.2W
Linux up, wifi connected to 2.4GHz and sending packet by iperf3
5V
400mA
2W
Linux up, wifi connected to 5GHz and sending packet by iperf3
5V
430mA
2.15W
Linux up, scanning for bluetooth device
5V
250mA
1.25W
Linux up, GPU stress by glmark2
5V
460mA
2.3W
Linux up, CPU stress to maximum
5V
400mA
2W
All utilities are active in the same time (Wifi, GPU stress, CPU stress, Bluetooth)
5V
670mA
3.35W
RZ/V2L Power Table
Mode
Voltage
Current
Power
Idle, Linux up
5V
240mA
1.2W
Linux up, wifi connected to 2.4GHz and sending packet by iperf3
5V
384mA
1.94W
Linux up, wifi connected to 5GHz and sending packet by iperf3
5V
427mA
2.135W
Linux up, scanning for bluetooth device
5V
255mA
1.275W
Linux up, GPU stress by glmark2
5V
480mA
2.4W
Linux up, CPU stress to maximum
5V
384mA
1.92W
Linux up, AI tested with web camera
5V
864mA
4.32W
All utilities are active in the same time (Wifi, GPU stress, CPU stress, Bluetooth)
5V
528mA
2.64W
RESET
The PMIC generates the POR. A reset signal (PMIC_CRST_IN#) from the carrier board can generate a POR.
The PMIC supports a Power ON/OFF* signal to disable/enable all power signals besides RTC.
The PMIC supports an RTC that can be powered by a battery (J7-63).
(*) Note – The PMIC enables the power at Power-Up (No need to push the ON/OFF).
RZG2L/V2L INTEGRATION MANUAL
POWER UP SEQUENCE
A single 5V input sources the RZG2L/V2L. The PMIC supports all power sequences.
When using the SOM 3.3V output there is no need to consider its power sequence. If an external power source is used for the 3.3V, it must be powered according to the power sequence rules. (See RZG2L/V2L datasheet for details)
BOOTING OPTIONS
Strap pins Booting
The RZG2L/V2L boost from different NVM or serial interfaces according to external resistors setting. The boot configuration is set by the three configuration signals (MD0, MD1, and MD2) and a selection signal (SD0_DEV_SEL) that select between eMMC and uSD (Mux on SOM). Below is a table describing the configuration modes.
MD2 J5001-41
MD1 J5001-5
MD0 J5001-3
SD0_DEV_SEL J9-64
MODE
0
0
0
0
uSD (Start up 3.3V)
0
0
1
1
eMMC (1.8V)
0
1
1
N/A
SPI Single/Quad/Octal (1.8V)
1
0
1
N/A
SCIF Download
Note – There are setting resistors on the SOM, but they are not assembled in the default configuration. Setting is done on the carrier board.
I2C INTERFACES
The RZG2L/V2L uses I2C2 (PMIC) interfaces for its internal configurations.
GPIO INTERFACES
The RZG2L/V2L SOM uses some GPIO signals for its internal controls. The following table describes the GPIO allocation.
Signal
I/O
Description
Remarks
ENET_nINT
P27_0
Ethernet interrupt
Active Low
ENET1_nINT
P42_4
Ethernet 1 interrupt
Active Low
WL_REG_ON
P23_1
Enable the WLAN
Active High
BT_REG_ON
P23_0
Enable the BT
Active High
Mechanical Description
Following is a diagram of the TOP VIEW of the RZG2L/V2L.
SOM Version Changes:
SOM Version
SOM Version Changes
1.0
Prototype Version
1.1
1. Swapping between TX_CLK and TX_CTL in the Ethernet PHYs 2. Connecting ETH0 power to 3V3
1.2
1. Connect the WIFI clock (PMIC_32KHz_CLK) to Pull Up 2. Move RZ_P5_1 from J7-33 to J7-13 to support M.2 Reset on the HBP 3. Move RZ_P5_0 from J7-39 to J7-15 4. Move RZ_P5_2 from J7-37 to J7-8 5. Enable power control from BtB. Adding U14 (PU/PD select) 6. Move RZ_P16_0 from J7-59 to J7-79 7. Add AUDIO_CLK to J7-59 8. Add R116 to support RTC clock from MPIO2. 9. Swapping I2C1 pins on J9: J9-51-SDA, J9-53-SCL.
Documentation
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