LX2162A SOM Hardware User Manual
Revisions and Notes
Date
Owner
Revision
Notes
27 Mar 2022
Rabeeh Khoury
1.0
May 15, 2023
Rabeeh Khoury
1.1
- Limited DDR4 configuration to 8 and 16GByte only (removed 32GByte support). - Added notes withregards max power consumption
No warranty of accuracy is given concerning the contents of the information contained in this publication. To the extent permitted by law no liability (including liability to any person by reason of negligence) will be accepted by SolidRun Ltd., its subsidiaries or employees for any direct or indirect loss or damage caused by omissions from or inaccuracies in this document. SolidRun Ltd. reserves the right to change details in this publication without prior notice. Product and company names herein may be the trademarks of their respective owners.
Introduction
This document is intended for hardware engineers that are willing to integrate
LX2162A SOM module from SolidRun ltd.
The document provides details with regards LX2162A module rev 1.0.
Below are two pictures of the SOM; the first is the top side where most of the heat is generated; and the second is from the bottom side where it connects to a carrier board -
Specifications
LX2082A
LX2122A
LX2162A
CPU Details
NXP Layerscape LX2082A 8 x Cortex A72
NXP Layerscape LX2122A 12 x Cortex A72
NXP Layerscape LX2162A 16 x Cortex A72
CPU Speed
2.0GHz Commercial
2.0GHz Commercial
2.0GHz Commercial
RAM
Single channel with 8GB or 16GB DDR4
Single channel with 8GB or 16GB DDR4
Single channel with 8GB or 16GB DDR4
Internal Storage
8GB eMMC 64MB SPI (other ordering options available)
8GB eMMC 64MB SPI (other ordering options available)
8GB eMMC 64MB SPI (other ordering options available)
External Storage Support
SD PCIe-SSD
SD PCIe-SSD
SD PCIe-SSD
Ethernet
Serdes block 1 (4x25 GbE / 1x100 GbE / 4x10GbE) Serdes block 2 (8x1GbE)(*) Sync-E, 1588-V2 1GbE with PHY
Serdes block 1 (4x25 GbE / 1x100 GbE / 4x10GbE) Serdes block 2 (8x1GbE)(*) Sync-E, 1588-V2 1GbE with PHY
Serdes block 1 (4x25 GbE / 1x100 GbE / 4x10GbE) Serdes block 2 (8x1GbE)(*) Sync-E, 1588-V2 1GbE with PHY
USB 3.0
1
1
1
PCIe
8 (Gen 3 – 2 controllers)*
8 (Gen 3 – 2 controllers)*
8 (Gen 3 – 2 controllers)*
I2C
4
4
4
UART
2
2
2
GPIO
✔
✔
✔
SATA
4xGen 3(*)
4xGen 3(*)
4xGen 3(*)
Security
NXP Layerscape Secure Boot
NXP Layerscape Secure Boot
NXP Layerscape Secure Boot
SD
1
1
1
JTAG
✔
✔
✔
OS Support
Linux DPDK UEFI
Linux DPDK UEFI
Linux DPDK UEFI
Size
55 x 48 mm
55 x 48 mm
55 x 48 mm
Interface
3 x Hirose DF40 connectors
3 x Hirose DF40 connectors
3 x Hirose DF40 connectors
Main Voltage
12V
12V
12V
I/O Voltage
3.3V/1.8V
3.3V/1.8V
3.3V/1.8V
Temperature
Commercial: 0°C to 70°C
Commercial: 0°C to 70°C
Commercial: 0°C to 70°C
Humidity
Humidity (non-condensing): 10% – 90%
Humidity (non-condensing): 10% – 90%
Humidity (non-condensing): 10% – 90%
(*) Configurable SD2 SERDESs based on NXP LX2162A processor specifications.
Overview
LX2162A SOM is a highly integrated SOM module based on NXP’s LX2162A SoC.
The SoC highlights are up to 2.0GHz 16 x Cortex A72 Arm cores, DDR4 2900 MT/s up to 16 GB capacity with ECC and 12 high speed SERDESes.
The module integrates the following features –
LX2162A SoC (up to 2.0GHz).
On-board single controller supports up to 16GByte DDR4 2900Mtps memory with and without ECC.
Single 12V DC-input is required.
Description
Block Diagram
The following figure describes the LX2162A SOM Blocks Diagram.
Simplified Schematics
Following is a link to that simplified schematics of the board : LX2162A COM Simplified Schematics
LX2162A SOM simplified schematics is intended for the following audience –
Software and firmware engineers that enables them to understand the IO and signal connectivity of the SOM design.
Hardware engineers that are willing to use the SOM and build their own development board.
Module dimensions and board to board header orientation
SOM bottom side DXF file - use attached dxf file for board dimensions, mounting holes and board to board connectors location
*note the board to board pin numbers and keep in mind this is bottom view
Module Max Power Consumption Measurements
Worst case scenario measured, power consumption wise was ~35W on the following scenario -
SOM attached to a simple carrier baseboard
Measured the 12v power rail coming to the whole system
Running 16 threads cpuburn application or memtester application on all cores
CPU junction temperature set to max at 105c
Test excludes SERDES connection, so additional 2-3W for SERDES connections must be taken into account.
SERDES configuration
LX2162A has 2 configurable SERDES blocks named SD1, and SD2.
SERDES 1 block has 4 SERDESes, and SERDES 2 block has 8 SERDESes that can be configured by protocol number. The protocol numbers are limited and can be selected from the following configurations –
SERDES block #1 (SD1)
Protocol
Lane 0 10G-KR0
Lane 1 10G- KR1
Lane 2 10G-KR2
Lane 3 10G-KR3
0
off
off
off
off
1 (*)
PCIe.1 x4
2 (*)
SGMII.3
SGMII.4
SGMII.5
SGMII.6
3
USXGMII / XFI.3
USXGMII / XFI.4
USXGMII / XFI.5
USXGMII / XFI.6
9 (*)
PCIe.1 x1
SGMII.4
SGMII.5
SGMII.6
11 (*)
PCIe.1 x2
SGMII.5
SGMII.6
15
50GE.1
50GE.2
16
50GE.1
25GE.5
25GE.6
17
25GE.3
25GE.4
25GE.5
25GE.6
18
USXGMII / XFI.3
USXGMII / XFI.4
25GE.5
25GE.6
20
40GE.1
(*) Contact SolidRun for this option - requires assembling 100MHz reference clock for SD1 PLLF instead of default 161.13285MHz reference clock
(*) As a self-service the customer can modify the default REFDES U10 that is 161.13285MHz differential clock which is Epson PN X1G004251012100 to Epson PN SG3225EAN 100.000000M-KEGA3. The placement of U10 is as below - (pin 1 marked in red dot) -
SERDES block #2 (SD2)
Protocol
Lane 0 10G-KR0
Lane 1 10G- KR1
Lane 2 10G-KR2
Lane 3 10G-KR3
Lane 4 PCIe16
Lane 5 PCIe17
Lane 6 PCIe18
Lane 7 PCIe19
0
off
off
off
off
off
off
off
off
1
PCIe.3 x 2 (gen 1,2)
SATA.1
SATA.2
PCIe.4 x4 (gen 1,2)
2
PCIe.3 x8
3
PCIe.3 x4
PCIe.4 x4
4
PCIe.3 x4 (gen 1,2)
PCIe.4 x2 (gen 1,2)
SATA.1
SATA.2
5
PCIe.3 x4
SATA.3
SATA.4
SATA.1
SATA.2
6
PCIe.3 x4 (gen 1,2)
SGMII.15
SGMII.16
USXGMII / XFI.13
USXGMII / XFI.14
7
PCIe.3 x1 (gen 1,2)
SGMII.12
SGMII.17
SGMII.18
PCIe.4 x1 (gen 1,2)
SGMII.16
USXGMII / XFI.13
USXGMII / XFI.14
8
X
X
SATA.1
SATA.2
SATA.3
SATA.4
USXGMII / XFI.13
USXGMII / XFI.14
9
SGMII.11
SGMII.12
SGMII.17
SGMII.18
SGMII.15
SGMII.16
SGMII.13
SGMII.14
10
SGMII.11
SGMII.12
SGMII.17
SGMII.18
PCIe.4 x4
11
PCIe.3 x1
SGMII.12
SGMII.17
SGMII.18
PCIe.4 x1
SGMII.16
SGMII.13
SGMII.14
12
SGMII.11
SGMII.12
SGMII.17
SGMII.18
PCIe.4 x2 (gen 1,2)
SATA.1
SATA.2
13
PCIe.3 x4
PCIe.2 x2
SGMII.13
SGMII.14
14
PCIe.3 x2
SGMII.17
SGMII.18
PCIe.2 x2
SGMII.13
SGMII.14
Notice: By default SD2 PLLS is assembled as onboard 156.25MHz and an external 100MHz reference clock (HCSL) is required to be supplied by the carrier board. There is an option to order with an integrated 100MHz reference clock but will require special order from SolidRun.
Pinout
J3 Header
Notes
Driving IC
IC ball number
Schematics Pin Name
Pin Number
Pin Number
Schematics Pin Name
IC ball number
Driving IC
Notes
Can be floated, or pulled to GND until carrier board powers are valid
PWR_OK
2
1
EVT0_B
T4
1.8V, GPIO_3[12], 4.7K Pull-up
SMB_ALERT#
Connect to RTC battery source
VBAT
4
3
EVT1_B
T6
1.8V, GPIO_3[13], 4.7K Pull-up
THRM#
Output from SOM. Can be used by carrier board up to 600mA
5V
6
5
EVT2_B
U5
1.8V, GPIO_3[14], 4.7K Pull-up
Output from SOM. Can be used by carrier board up to 600mA
5V
8
7
EVT4_B
AA3
1.8V, GPIO_3[16], 4.7K Pull-up
PROC_TMS
LX2162A
E21
DUT_TMS
10
9
EVT3_B
Y4
1.8V, GPIO_3[15], 4.7K Pull-up
PROC_TCK
LX2162A
E23
DUT_TCK
12
11
TA_BB_VDD
Output from SOM. Can be used by carrier board up to 300mA
3.3V
14
13
TMP_DETECT_B
Y6
1.8V, 4.7K Pull-up
PROC_TDI
LX2162A
F20
DUT_TDI
16
15
OVDD
1.8v Output from SOM. Can be used by carrier board up to 300mA
Control the main DC-DC controller
I2C_MASTER_SCL
18
17
V_2.5
Output from SOM. Can be used by carrier board up to 600mA
Control the main DC-DC controller
I2C_MASTER_SDA
20
19
V_2.5
PROC_TDO
LX2162A
E19
DUT_TDO
22
21
I2C1_SCL_3p3
NTSX2102GD, 2.2K Pull-up
Can be used to program the internal efuses
TA_PROG_SFP
24
23
I2C1_SDA_3p3
NTSX2102GD, 2.2K Pull-up
FTM1_CH4 / GPIO_3[0]
1.8V, 4.7K Pull-up
R5
PROC_IRQ0
26
25
SPI_D0_1v8
SPI_MUX_1v8_3v3
28
27
SPI_D1_1v8
SPI_CS_B_1v8
30
29
SPI_SCK_1v8
J2 Header
Notes
Driving IC
IC ball number
Schematics Pin Name
Pin Number
Pin Number
Schematics Pin Name
IC ball number
Driving IC
Notes
Diff 100 Ohm
AR8035
MDI_P0
2
1
12V
Single 12v input to SOM . Can be up to 15V
Diff 100 Ohm
AR8035
MDI_N0
4
3
12V
GND
6
5
12V
Diff 100 Ohm
AR8035
MDI_P1
8
7
12V
Diff 100 Ohm
AR8035
MDI_N1
10
9
12V
GND
12
11
12V
Diff 100 Ohm
AR8035
MDI_P2
14
13
12V
Diff 100 Ohm
AR8035
MDI_N2
16
15
12V
GND
18
17
GND
Diff 100 Ohm
AR8035
MDI_P3
20
19
SYS_RESET_IN_1v8#
PT7M3808G01
1.8v system reset input
Diff 100 Ohm
AR8035
MDI_N3
22
21
SYSRST_OUT_3v3#
MC74VHC1GT08
3.3v system reset out
GND
24
23
PROC_EC2_RXD0
AW3
LX2162A
TSEC_1588_TRIG_IN2 / GPIO_4[21]
AR8035
GBE0_LINK1000#
26
25
PROC_EC2_RXD1
AV2
LX2162A
TSEC_1588_PULSE_OUT1 / GPIO_4[20]
AR8035
GBE0_ACT#
28
27
PROC_EC2_RXD2
AU1
LX2162A
GPIO_4[19]
AR8035
GBE0_LINK#
30
29
PROC_EC2_RXD3
AR1
LX2162A
GPIO_4[18]
Used for boot select
1.8V, CFG_RCW_SRC3, 10K Pull-up
AH6
CFG_RCW_SRC3
32
31
PROC_EC2_RX_CLK
AR3
LX2162A
TSEC_1588_CLK_IN / GPIO_4[22]
CFG_RCW_SRC0 Used for boot select
LX2162A
AH4
UART2_TXD_1v8
34
33
GND
LX2162A
AE3
UART2_RXD_1v8
36
35
I1588_TRIG_IN1
AW1
LX2162A
TSEC_1588_TRIG_IN1 / GPIO_4[23]
PWRBTN#
1.8V, GPIO3[6], 4.7K Pull-up
PROC_IRQ6
38
37
I1588_ALARM_OUT2
AR5
LX2162A
TSEC_1588_ALARM_OUT2 / GPIO_4[12]
ASLEEP / EVT9_B / GPIO_2[6] Used for boot select
1.8V, 10K Pull-up
AC1
CFG_RCW_SRC2
40
39
I1588_CLK_OUT
AU3
LX2162A
TSEC_1588_CLK_OUT / GPIO_4[14] / EC2_TXD1_S
LX2162A_RCLK0
AV6
IEEE_RCLK0
42
41
I1588_PULSE_OUT2
AU5
LX2162A
TSEC_1588_PULSE_OUT2 / GPIO_4[15] / EC2_TXD0_S
LX2162A_RCLK1
AT6
IEEE_RCLK1
44
43
I1588_ALARM_OUT1
AT4
LX2162A
TSEC_1588_ALARM_OUT1 / GPIO_4[13] / EC2_TXD2_S
GPIO_3[10]
1.8V, 4.7K Pull-up
U3
PROC_IRQ10
46
45
UART1_TXD_1v8
AD4
LX2162A
CFG_RCW_SRC1 Used for boot select
SUS_S5#
1.8V, 4.7K Pull-up
R1
PROC_IRQ7
48
47
UART1_RXD_1v8
AC3
LX2162A
1.8V, 2.2K Pull-up
AG1
EMI2_MDC
50
49
PROC_IRQ11
U1
LX2162A
1.8V, 2.2K Pull-up
AG3
EMI2_MDIO
52
51
EMI1_3V3_MDC
NTSX2102GD
LX2162A
W5
TA_BB_TMP_DETECT_B
54
53
EMI1_3V3_MDIO
NTSX2102GD
GPIO_4[17] / EC2_GTX_CLK_S
LX2162A
AP6
PROC_EC2_GTX_CLK
56
55
FAN_TACHIN
GND
58
57
PROC_EC2_TX_EN
AV4
LX2162A
GPIO_4[16] / EC2_TX_CTL_S
NVT4857UK
SD_CMD
60
59
PROC_IRQ9
AA1
1.8V, 4.7K Pull-up
NVT4857UK
SD_D0
62
61
PROC_IRQ5
W1
1.8V, 4.7K Pull-up
NVT4857UK
SD_D1
64
63
PROC_IRQ1
P2
1.8V, 4.7K Pull-up
NVT4857UK
SD_D2
66
65
I2C3_SCL
P6
LX2162A
NVT4857UK
SD_D3
68
67
I2C3_SDA
N6
LX2162A
NVT4857UK
SD_CD
70
69
I2C5_SDA
K2
LX2162A
NVT4857UK
SD_CLK
72
71
I2C5_SCL
J1
LX2162A
Diff 90 Ohm
LX2162A
A5
USB_SSRX0+
74
73
USB0+
A9
LX2162A
Diff 90 Ohm
Diff 90 Ohm
LX2162A
B6
USB_SSRX0-
76
75
USB0-
B10
LX2162A
Diff 90 Ohm
Diff 90 Ohm
LX2162A
A7
USB_SSTX0+
78
77
GND
Diff 90 Ohm
LX2162A
B8
USB_SSTX0-
80
79
FAN_PWM
J1 Header*
Notes
Driving IC
IC ball number
Schematics Pin Name
Pin Number
Pin Number
Schematics Pin Name
IC ball number
Driving IC
Notes
GND
2
1
GND
Diff 100 Ohm
LX2162A
BG7
SD1_RX3_P
4
3
SD1_TX3_P
BE9
LX2162A
Diff 100 Ohm (*)DC block capacitor required
Diff 100 Ohm
LX2162A
BH8
SD1_RX3_N
6
5
SD1_TX3_N
BD10
LX2162A
Diff 100 Ohm (*)DC block capacitor required
GND
8
7
GND
Diff 100 Ohm
LX2162A
BG5
SD1_RX2_P
10
9
SD1_TX2_P
BE7
LX2162A
Diff 100 Ohm (*)DC block capacitor required
Diff 100 Ohm
LX2162A
BH6
SD1_RX2_N
12
11
SD1_TX2_N
BD8
LX2162A
Diff 100 Ohm (*)DC block capacitor required
GND
14
13
GND
Diff 100 Ohm
LX2162A
BC1
SD1_RX1_P
16
15
SD1_TX1_P
BC5
LX2162A
Diff 100 Ohm (*)DC block capacitor required
Diff 100 Ohm
LX2162A
BD2
SD1_RX1_N
18
17
SD1_TX1_N
BD4
LX2162A
Diff 100 Ohm (*)DC block capacitor required
GND
20
19
GND
Diff 100 Ohm
LX2162A
BA1
SD1_RX0_P
22
21
SD1_TX0_P
BA5
LX2162A
Diff 100 Ohm (*)DC block capacitor required
Diff 100 Ohm
LX2162A
BB2
SD1_RX0_N
24
23
SD1_TX0_N
BB4
LX2162A
Diff 100 Ohm (*)DC block capacitor required
GND
26
25
GND
Diff 100 Ohm
LX2162A
BG9
SD2_RX0_P
28
27
SD2_TX0_P
BE11
LX2162A
Diff 100 Ohm (*)DC block capacitor required
Diff 100 Ohm
LX2162A
BH10
SD2_RX0_N
30
29
SD2_TX0_N
BD12
LX2162A
Diff 100 Ohm (*)DC block capacitor required
GND
32
31
GND
Diff 100 Ohm
LX2162A
BG11
SD2_RX1_P
34
33
SD2_TX1_P
BE13
LX2162A
Diff 100 Ohm (*)DC block capacitor required
Diff 100 Ohm
LX2162A
BH12
SD2_RX1_N
36
35
SD2_TX1_N
BD14
LX2162A
Diff 100 Ohm (*)DC block capacitor required
GND
38
37
GND
Diff 100 Ohm
LX2162A
BG13
SD2_RX2_P
40
39
SD2_TX2_P
BE15
LX2162A
Diff 100 Ohm (*)DC block capacitor required
Diff 100 Ohm
LX2162A
BH14
SD2_RX2_N
42
41
SD2_TX2_N
BD16
LX2162A
Diff 100 Ohm (*)DC block capacitor required
GND
44
43
GND
Diff 100 Ohm
LX2162A
BG15
SD2_RX3_P
46
45
SD2_TX3_P
BE17
LX2162A
Diff 100 Ohm (*)DC block capacitor required
Diff 100 Ohm
LX2162A
BH16
SD2_RX3_N
48
47
SD2_TX3_N
BD18
LX2162A
Diff 100 Ohm (*)DC block capacitor required
GND
50
49
GND
Diff 100 Ohm / SD2_PLLF_REF_CLK_P
*100M HCSL required
BG19
CLK_SLOT1_P
52
51
CLK_161_BYP_P
Not Connected
Diff 100 Ohm/ SD2_PLLF_REF_CLK_N
*100M HCSL required
BH20
CLK_SLOT1_N
54
53
CLK_161_BYP_N
Not Connected
GND
56
55
GND
Diff 100 Ohm
LX2162A
BG23
SD2_RX4_P
58
57
SD2_TX4_P
BE23
LX2162A
Diff 100 Ohm (*)DC block capacitor required
Diff 100 Ohm
LX2162A
BH24
SD2_RX4_N
60
59
SD2_TX4_N
BD24
LX2162A
Diff 100 Ohm (*)DC block capacitor required
GND
62
61
GND
Diff 100 Ohm
LX2162A
BG25
SD2_RX5_P
64
63
SD2_TX5_P
BE25
LX2162A
Diff 100 Ohm (*)DC block capacitor required
Diff 100 Ohm
LX2162A
BH26
SD2_RX5_N
66
65
SD2_TX5_N
BD26
LX2162A
Diff 100 Ohm (*)DC block capacitor required
GND
68
67
GND
Diff 100 Ohm
LX2162A
BG27
SD2_RX6_P
70
69
SD2_TX6_P
BE27
LX2162A
Diff 100 Ohm (*)DC block capacitor required
Diff 100 Ohm
LX2162A
BH28
SD2_RX6_N
72
71
SD2_TX6_N
BD28
LX2162A
Diff 100 Ohm (*)DC block capacitor required
GND
74
73
GND
Diff 100 Ohm
LX2162A
BG29
SD2_RX7_P
76
75
SD2_TX7_P
BE29
LX2162A
Diff 100 Ohm (*)DC block capacitor required
Diff 100 Ohm
LX2162A
BH30
SD2_RX7_N
78
77
SD2_TX7_N
BD30
LX2162A
Diff 100 Ohm (*)DC block capacitor required
GND
80
79
GND
*No DC blocking capacitor on any of the SerDes lanes on the SOM.
Accessing JTAG
See LX2162A SoM JTAG for details.
Documentation
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