LX2160A COM Hardware User Manual

Revisions and Notes

Date	Owner	Revision	Notes
08 Jan 2019	Rabeeh Khoury	1.0
May 2, 2023	Rabeeh Khoury	1.1	Updated notes about I2C pull-ups - - All I2C are 2.2k pulled-up from root I2C bus before I2C mux. All leaf I2C busses are 10k pulled-up - B13,B14,B33 and B44 are 2.2k pulled-up.
Feb 19, 2024	Rabeeh Khoury	1.2	Updated COM express 3D model to PCB rev 2.1
Oct 9, 2024	Josua Mayer	1.3	Updated PTP & Sync-E signal names to match LX2160 Datasheet
Nov 4, 2024	Josua Mayer	1.4	Added assembly option and component locations for PTP & Sync-E (not CEX-7 spec)
Oct 9, 2025	Rabeeh Khoury	1.5	Removed simplified schematics version 1.6 and kept latest version 2.1 Fixed typo of IEEE_RCLK0

No warranty of accuracy is given concerning the contents of the information contained in this publication. To the extent permitted by law no liability (including liability to any person by reason of negligence) will be accepted by SolidRun Ltd., its subsidiaries or employees for any direct or indirect loss or damage caused by omissions from or inaccuracies in this document. SolidRun Ltd. reserves the right to change details in this publication without prior notice. Product and company names herein may be the trademarks of their respective owners.

Introduction

This document is intended for hardware engineers that are willing to integrate

LX2160A COM express type 7 module from SolidRun ltd.

The document provides details with regards LX2160A module rev 1.3, 1.4, 1.5 and 1.6.

Specifications

Form Factor	COM Express type 7
Processor Core	16 core Arm Cortex A72
Processor speed	Up to 2GHz
Memory	Dual channel SO-DIMM DDR4; up to 64GB 2900MT/s (not included by default)*
ECC	Optional
eMMC	64GB by default (up to 128GB) 64MB SPI memory
SATA	2 x SATA (Gen III)**
Security	NXP LX2160A Secure Boot
Supported OS	Linux kernel 4.14x Yocto DPDK UEFI KVM/QEMU/Containers NFV Openstack compute node
XFI/RXAUI/SGMII	4**
PCIe gen 3.0	18 (5 controllers)**
SGMII	1 with built in phy
USB 3.0	4
I2C	6
UART	2
SPI bus	✓
Power	12V (9V-15V) 50W full system
Environment	Commercial: 0°C to 70°C Industrial: -40°C to 85°C Humidity (non-condensing): 10% – 90%
Dimensions	125mm X 95mm
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Overview

LX2160A COM express type 7 is a highly integrated COM modules based on NXP’s LX2160A SoC.

The SoC highlights are up to 2.2GHz 16 x Cortex A72 Arm cores, two DDR4 controllers up to 3200Mtps and 24 high speed SERDESes.

The module integrates the following features –

1. LX2160A SoC (up to 2.0GHz).
2. Two SO-DIMM DDR4 connected to the two DDR contorllers. Each SO-DIMM supports up to 32GByte SO-DIMM DDR4 2900Mtps memory with and without ECC, registered or non-registered; total up to 64GByte system memory.
3. Single 12v DC-input is required.

The higher 2.2GHz / DDR4-3200 SoC variant is only available on special request under MoQ.

Description

Block Diagram

The following figure describes the LX2160A COM express type 7 Blocks Diagram.

Simplified Schematics

Look below in the documentation section for the LX2160A COM express type 7 simplified schematics. LX2160A COM express type 7 simplified schematics is intended for the following audience –

1. Software and firmware engineers that enables them to understand the IO and signal connectivity of the COM express design.
2. Hardware engineers that are willing to use the COM express and build their own development board. This document completes the CEx7 LX2160A reference manual from description of signal and implementation wise.

S-Parameters

Browse below in the Documentation section in other files section to download LX2160A-CEX7 S-parameters.

The 25 GbE files refer to the 10G KR signals – total 32 ports model up to 20GHz and the second PCIe file refers to all other SERDESes while the model is up to 6GHz.

The S-parameters models includes the PCB extraction with the COM express header AND receptacle based on models from EPT.

Module Power Consumption Measurements

The following power consumption measurements were conducted on the following setup –

1. HoneyComb LX2 mini-ITX motherboard with pico-psu ATX power source
2. LX2160A COM express type 7 module connected running at 2GHz core, 700 MHz fabric and 3200Mtps DDR
3. Two SO-DIMM DDR4 at 3200Mtps (total 2x8GB = 16GByte system memory)
4. During the tests an 1.3Watt fan mounted on the processor. The idle, memtester and first cpu-burn power measurements below includes those 1.3Watt, the measurements with die temperature of 65c and above has the fan disconnected.
5. Temperature measurement was done using Linux ‘sensors’ commands, that reads both the PCB (print side of the board away from the center) and the processor die temperature.
6. Software running is based on NXP LSDK-19.06 software release.
7. A 12v PSU is connected to a pico-psu (12v to ATX); and power is measured by multiplying the current and the voltage on the 12v input rail.

Since the measurement is done on the input of the pico-psu; the SoC consumption all together with the DDR and all the DC-DC losses are measured too.

Test	Power (Watt)	PCB Temperature (Celsius)	Die Temperature (Celsius)
Linux idle	21.5	40	44.6
16x memtester 100M (*)	36.5	48	56.9
2x cpuburn-krait (**)	35.6	48.4	59.1
2x cpuburn-krait (***) – no fan	40.1	78.8	105

Please note (*) – The Linux command is ‘memtester 100M > /dev/null &’ ran 16x times where 16 is the core count (**) – The Linux command ‘cpuburn-krait’ is ran two times in background. The reason cpuburn-krait was chosen since it can generate most heat out of the cores (the core pipeline most utilized). (***) – This measurement was taken when the fan is disconnected and the power was measured when the die reached 105c. Notice that keeping the fan disconnected will make the processor reach temperatures that are out of spec.

Maximum Current Consumption

The LX2160A type 7 uses only the 12v power rail to supply it’s internal components.

The user of this module must make sure that the 12v power rail provided to the COM can sustain 5A, i.e. total 60W.

Notice the above section on power measurement using memtester and cpuburn applications which is worst case scenario of ~40@ when the core junction is at 105c; taking into account different SO-DIMMs used and variance in processor leakage due to silicon manufacturing environments, we recommend to design the carrier board to sustain those 5A on the 12V rail.

PCIe Lane Numbers and Bucket Grouping

Following is the bucket grouping of the different PCIe lanes.

Bucket B1 – lanes #0 .. #7

There is a single configuration in this bucket –

x4 PCIe lanes 0,1,2,3 connected to controller #3 (SERDES SD2 lanes 0,1,2,3)

x2 PCIe lanes 4,5 connected to controller #4 (SERDES SD2 lanes 4,5)

PCIe lanes 6,7 are NC

• Notice that it is possible to gang PCIe lanes 0..5 with SATA0 and SATA1 and which makes all SD2 lanes 0..7 and have a single x8 gen3 controller #3. In this configuration the on COM module DC bias serial capacitors are required to be changed to 220nF instead of 10nF (contact SolidRun for more information)

Bucket B2 – lanes #8 .. #15

There are two possible configurations in this bucket –

1. 2 times x4 – Lanes 8 to 11 connected to controller #5 and lanes 12 to 15 connected to controller #6.
2. 1 time x8 -Lanes 8 to 15 are connected to controller #5

Bucket B3 – lanes #16 .. #23

There is a single configuration in this bucket –

1. Up to 1 time x4 – lanes 16 .. 19 on controller #2. Lanes 20 to 23 are NC.

• Notice that this configuration highly depends on the SD1 SERDES protocol number configuration. Please follow SD1 protocol number configuration in this document that explains how those lanes are affected.

Bucket B4 – lanes #24 .. #31

All lanes in this bucket are NC.

SERDES configuration

LX2160A has 3 SERDES blocks named SD1, SD2 and SD3.

SERDES block #1 (SD1)

SERDES block #1 (SD1) has the most different options to configure from. By default the board is assembled with PLLF=161.1328125MHz and PLLS=100MHz, spread spectrum disabled.

In order to swap both PLLF and PLLS to be 100MHz:

• Move C996 and C997 to C80 and C81 (same value 100nF low ESL 0402 capacitor). This will move the 161.1328125MHz from PLLF to PLLS
• Move R383 and R384 to R381 and R382 (zero ohm 0402 resistors). This will move the 100MHz reference clock from PLLS to PLLF

** these capacitors/resistors have shared pads as shown in the picture below

Each SERDES block has 8 SERDESes that can be configured by protocol number.

Noticve: The Default clock assembly limits the amount of configurations according to the table below:

Protocol	Lane 0 10G-KR0	Lane 1 10G- KR1	Lane 2 10G-KR2	Lane 3 10G-KR3	Lane 4 PCIe16	Lane 5 PCIe17	Lane 6 PCIe18	Lane 7 PCIe19	Notes
0	off	off	off	off	off	off	off	off
1	PCIe.1 x4				PCIe.2 x4				(*)
2	SGMII.3	SGMII.4	SGMII.5	SGMII.6	PCIe.2 x4				(*)
7	XFI.3	XFI.4

AB Header

	Notes	Driving IC	Schematics Pin Name	Pin Number	Pin Number	Schematics Pin Name	Driving IC	Notes
1			GND (FIXED)	A1	B1	GND (FIXED)
2		AR8035	GBE0_MDI3-	A2	B2	GBE0_ACT#	AR8035 LED_ACT
3		AR8035	GBE0_MDI3+	A3	B3	LPC_FRAME#
4	Not used		GBE0_LINK100#	A4	B4	LPC_AD0
5		AR8035 LED_1000 pin 22	GBE0_LINK1000#	A5	B5	LPC_AD1
6		AR8035	GBE0_MDI2-	A6	B6	LPC_AD2
7		AR8035	GBE0_MDI2+	A7	B7	LPC_AD3
8		AR8035 LED_10_100 pin 24	GBE0_LINK#	A8	B8	LPC_DRQ0#
9		AR8035	GBE0_MDI1-	A9	B9	LPC_DRQ1#
10		AR8035	GBE0_MDI1+	A10	B10	LPC_CLK
11			GND (FIXED)	A11	B11	GND (FIXED)
12		AR8035	GBE0_MDI0-	A12	B12	PWRBTN#	3.3v, GPIO3[6], 2.2k pull-up
13		AR8035	GBE0_MDI0+	A13	B13	SMB_CK	I2C1 - CH#3	2.2k pulled-up
14	Not used		GBE0_CTREF	A14	B14	SMB_DAT	I2C1 - CH#3	2.2k pulled-up
15			SUS_S3#	A15	B15	SMB_ALERT#	3.3v, EVT0, GPIO3[12], 2.2k pull-up
16	Serial 10nF	LX2160A SD2 SRDS6	SATA0_TX+	A16	B16	SATA1_TX+	LX2160A SD2 SRDS7	Serial 10nF
17	Serial 10nF	LX2160A SD2 SRDS6	SATA0_TX	A17	B17	SATA1_TX	LX2160A SD2 SRDS7	Serial 10nF
18			SUS_S4#	A18	B18	SUS_STAT#
19	Serial 10nF	LX2160A SD2 SRDS6	SATA0_RX+	A19	B19	SATA1_RX+	LX2160A SD2 SRDS7	Serial 10nF
20	Serial 10nF	LX2160A SD2 SRDS6	SATA0_RX	A20	B20	SATA1_RX	LX2160A SD2 SRDS7	Serial 10nF
21			GND (FIXED)	A21	B21	GND (FIXED)
22	Serial 220nF	LX2160A SD3 SRDS7	PCIE_TX15+	A22	B22	PCIE_RX15+	LX2160A SD3 SRDS7
23	Serial 220nF	LX2160A SD3 SRDS7	PCIE_TX15-	A23	B23	PCIE_RX15-	LX2160A SD3 SRDS7
24	3.3v, GPIO3[7], 2.2k pull-up		SUS_S5#	A24	B24	PWR_OK	Power management IC	Refer to power-up sequence
25	Serial 220nF	LX2160A SD3 SRDS6	PCIE_TX14+	A25	B25	PCIE_RX14+	LX2160A SD3 SRDS6
26	Serial 220nF	LX2160A SD3 SRDS6	PCIE_TX14-	A26	B26	PCIE_RX14+	LX2160A SD3 SRDS6
27	3.3v, EVT4, GPIO3[16], 2.2k pull-up		BATLOW#	A27	B27	WDT
28			SATA_ACT#	A28	B28	RSVD
29			RSVD	A29	B29	RSVD
30			RSVD	A30	B30	RSVD
31			GND (FIXED)	A31	B31	GND (FIXED)
32			RSVD	A32	B32	SPKR
33			RSVD	A33	B33	I2C_CK	LX2160A I2C2	2.2k pulled-up
34	SPI CS0/1 switch, 3.3v, 2.2k pull-up		BIOS_DIS0#	A34	B34	I2C_DAT	LX2160A I2C2	2.2k pulled-up
35			THRMTRIP#	A35	B35	THRM#	3.3v, EVT1, GPIO3[13], 2.2k pull-up
36	Serial 220nF	LX2160A SD3 SRDS5	PCIE_TX13+	A36	B36	PCIE_RX13+	LX2160A SD3 SRDS5
37	Serial 220nF	LX2160A SD3 SRDS5	PCIE_TX13-	A37	B37	PCIE_RX13-	LX2160A SD3 SRDS5
38			GND	A38	B38	GND
39	Serial 220nF	LX2160A SD3 SRDS4	PCIE_TX12+	A39	B39	PCIE_RX12+	LX2160A SD3 SRDS4
40	Serial 220nF	LX2160A SD3 SRDS4	PCIE_TX12-	A40	B40	PCIE_RX12+	LX2160A SD3 SRDS4
41			GND (FIXED)	A41	B41	GND (FIXED)
42		USB3.0 HUB port 2	USB2-	A42	B42	USB3-	USB3.0 HUB port 3
43		USB3.0 HUB port 2	USB2+	A43	B43	USB3+	USB3.0 HUB port 3
44			USB_2_3_OC#	A44	B44	USB_0_1_OC#
45		LX2160A USB0	USB0-	A45	B45	USB1-	USB3.0 HUB port 1
46		LX2160A USB0	USB0+	A46	B46	USB1+	USB3.0 HUB port 1
47	100nF and 22uF on module	PCF2129AT	VCC_RTC	A47	B47	ESPI_EN
48			RSVD	A48	B48	RSVD
49		LX2160A TSEC_1588_TRIG_IN1 - Only rev 1.6 and newer; 1.8v signal; assembly-option.	RSVD	A49	B49	SYS_RESET#	3.3v, 2.2k pull-up, sys reset input
50			LPC_SERIRQ	A50	B50	CB_RESET#	3.3v, carrier board reset output (1uF capacitance)
51			GND (FIXED)	A51	B51	GND (FIXED)
52	Serial 220nF	LX2160A SD2 SRDS5	PCIE_TX5+	A52	B52	PCIE_RX5+	LX2160A SD2 SRDS5
53	Serial 220nF	LX2160A SD2 SRDS5	PCIE_TX5-	A53	B53	PCIE_RX5-	LX2160A SD2 SRDS5
54		micro SD D0	GPI0	A54	B54	GPO1	micro SD CMD
55	Serial 220nF	LX2160A SD2 SRDS4	PCIE_TX4+	A55	B55	PCIE_RX4+	LX2160A SD2 SRDS4
56	Serial 220nF	LX2160A SD2 SRDS4	PCIE_TX4-	A56	B56	PCIE_RX4-	LX2160A SD2 SRDS4
57			GND	A57	B57	GPO2	3.3v, GPIO3[5], 2.2k pull-up
58	Serial 220nF	LX2160A SD2 SRDS3	PCIE_TX3+	A58	B58	PCIE_RX3+	LX2160A SD2 SRDS3
59	Serial 220nF	LX2160A SD2 SRDS3	PCIE_TX3-	A59	B59	PCIE_RX3-	LX2160A SD2 SRDS3
60			GND (FIXED)	A60	B60	GND (FIXED)
61	Serial 220nF	LX2160A SD2 SRDS2	PCIE_TX2+	A61	B61	PCIE_RX2+	LX2160A SD2 SRDS2
62	Serial 220nF	LX2160A SD2 SRDS2	PCIE_TX2-	A62	B62	PCIE_RX2-	LX2160A SD2 SRDS2
63		micro SD D1	GPI1	A63	B63	GPO3/SD_CD	micro SD CD (2.2k 3.3v pulled-up)
64	Serial 220nF	LX2160A SD2 SRDS1	PCIE_TX1+	A64	B64	PCIE_RX1+	LX2160A SD2 SRDS1
65	Serial 220nF	LX2160A SD2 SRDS1	PCIE_TX1-	A65	B65	PCIE_RX1-	LX2160A SD2 SRDS1
66			GND	A66	B66	WAKE0#
67		micro SD D2	GPI2	A67	B67	WAKE1#
68	Serial 220nF