i.MX8M SOM Hardware User Manual

Revision and Notes

Date

Owner

Revision

Notes

18 Feb 2018

Noam Weidenfeld

1.0

Initial release

01 Aug 2019

Noam Weidenfeld

1.1

Revision update

Disclaimer No warranty of accuracy is given concerning the contents of the information contained in this publication. To the extent permitted by law no liability (including liability to any person by reason of negligence) will be accepted by SolidRun Ltd., its subsidiaries or employees for any direct or indirect loss or damage caused by omissions from or inaccuracies in this document. SolidRun Ltd. reserves the right to change details in this publication without prior notice. Product and company names herein may be the trademarks of their respective owners.

Introduction

This User Manual relates to the SolidRun SOM i.MX8M series, which includes:

Dual core ARM A53 (1.5 GHz) of the i.MX8M
Quad lite core ARM A53 (1.5GHz) of the i.MX8M
Quad core ARM A53 (1.5GHz) of the i.MX8M

Overview

The SolidRun’s SOM i.MX8M is a high-performance system on module (SOM) based on the highly integrated NXP i.MX8M family of products.

Highlighted Features

Ultra-small footprint SOM (47x30mm) including three board-to-board connectors (250 total pins number).
NXP i.MX8M SoC (supports dual, quad lite and quad versions)
- Up to quad Cortex A53 and up to 5GHz
- Cortex-M4 subsystem processor supports real time
- Industry-leading audio,voice and video processing for applications
- OpenGL ES 3.1, OpenCL 1.2, OpenGL 3.0, OpenVG and Vulkan standards
LPDDR4 memory in x32 configurations supports up to 4GB (Quad version)
Power management devices
Gigabit Ethernet interface based on Qualcomm Atheros 8031
Wi-Fi (11ac/b/g/n 2Tx2R) + BT (V4.1 LE) M.2 Type 1216 based on Qualcomm Atheros QCA6174A-5.
BT V5.0 based on Nordic’s nRF52832**.**
PCIe clock generator supporting
4-Lanes CSI connector for direct connection to a camera.

Supporting Products

The following products are provided from SolidRun both as production level platforms and as reference examples on how to incorporate the SOM in different levels of integration:

HummingBoard Pulse– A board computer that incorporates the SOM retains the same Android and different Linux distributions while adding extra hardware functionalities and access to the
CuBox Pulse – A minicomputer that is only 2″x2″x2″ in size that runs Android and Linux with different distribution variants, use cases.

Description

Block Diagram

The following figure describes the i.MX8M blocks diagram.

Feature Summary

Following is the features summary of the SOM. Notice that some of the features are pinout multiplexed (please refer to the pin mux table below and the NXP i.MX8M data sheets):

NXP i.MX8M series SoC (Dual/Quad Lite/Quad ARM® Cortex™ A53 Processor, up to 1.5 GHz)
Cortex-M4 subsystem
Up to 4GByte LPDDR4 memory
Eight bits eMMC
QSPI NOR Flash memory.
I2C
HDMI 2.0a, HDMI 1.4 interface
4-lanes MIPI-DSI interface
Two 4 lanes MIPI CSI-2 ()
10/100/1000 Mbps Ethernet PHY supporting 1588 standard (PPS output)
Wi-Fi (11ac/b/g/n 2Tx2R) + BT (V4.1 LE) M.2 Type 1216 based on Qualcomm Atheros QCA6174A-5.
BT V5.0 based on Nordic’s nRF52832
Two USB 3.0 Host and OTG
Two PCIe interfaces (PCIe-1 is available only if Wi-Fi is not inuse).
PCIe clock
Four bits SD interface
Single eSPI
Up to three Synchronous Audio
Up to three Serial
Required power sources:
- A single 5.0V interface
- 8/3.3V to support uSD card optional IO power.

Core System Components

i.MX8 SoC Family

The i.MX8M Dual / 8M QuadLite / 8M Quad processors feature advanced implementation of a quad Arm® Cortex®-A53 core, which operates at speeds of up to 1.5 GHz. A general- purpose Cortex®-M4 core processor is for low-power processing.

The following figure describes the i.MX8 SoC’s main features (For more details refer to NXP’s i.MX8 datasheet).

i.MX8M supports three variants; the following table describes the main differences:

Memory

The i.MX8M SOM support varieties of memory interfaces for booting and data storage. The following figure describes the i.MX8M SOM memory interfaces.

LPDDR4

Up to 4GB memory space (Quad-Lite and Dual up to 3GB).
32 Bits data
Up to 3200 MT/s.
Supports D1, D2 and D4 die chips (Two CS).
Support various low power modes, clock and power gated
Support Self-Refresh

eMMC NAND Flash

Up to 64GB memory
8 Bits data
Support MMC standard, up to version 0.
Up to 1600 Mbps of data transfer for MMC cards using 8 parallel data lines in SDR mode.
Up to 3200 Mbps of data transfer for MMC cards using 8 parallel data lines in DDR mode.
IMX-8 uSDHC-1.
Can be used as BOOT NVM *

Quad Serial NOR Flash (SOM)

Each channel can be configured as 1/2/4-bit
Support both SDR mode and DDR mode
No reset
IMX-8 QSPIA/nSS0.
Can be used as BOOT NVM *

EEPROM (SOM)

1Kb EEPROM
ON-Semi’s CAT24AA01TDI or compatible
IMX-6 I2C1
Address 0X50 (7 bits format)
Stores SOM’s

Micro-SD (Carrier)

Optional on Carrier board
IMX-8 uSDHC-1.
Implements 4 data
Support SD/SDIO standard, up to version 0.
Up to 400 Mbps of data transfer in SDR mode and up to 800 Mbps of data transfer in DDR mode using 4 parallel data
Can be used as BOOT NVM *

Serial NOR Flash (Carrier)

Optional on Carrier board
1 bits data
IMX-8 eSPI2/nSS0
Can be used as BOOT NVM *

Please Note All boot configuration signals are available on the SOM connector.

10/100/1000 MBPS Ethernet PHY

The Ethernet PHY is based on the Qualcomm / Atheros AR8031. The following figure describes the Giga Ethernet interface.

IMX-8 RGMII
IEEE 802.3 Ethernet interface for 1000BASE-T, 100BASE-TX, and 10BASE-Te.
Atheros AR8031
Supports 1588 (PPS signal).
25M clock supports Synchronous

WI-FI (11AC/B/G/N 2TX2R) TYPE 1216 AND BT 5.0

The following figure describes the WI-FI and BT support in the IMX-8 SOM.

WI-FI

The WI-FI module is an M.2 1216 standard LGA module. The i.MX8 WI-FI module is Silex’s

WCBN3507A which based on Qualcomm Atheros QCA6174A-5 chip. The WI-FI main features are:

Operate at ISM frequency Band (2.4/ 5 GHz)
IEEE Standards Support 802.11ac, 802.11a, 802.11b, 802.11g and 11n
IMX-8 PCIe-1 interface
Enterprise level security supporting: WPA, WPA2
Support 2 transmission and 2 receiving, transmission rate can up to 867Mbps(Physical Rate) in downstream and upstream
USB2 connection is optional from carrier board to support BT over the M.2 module (*).
Global

BT 5.0

The i.MX8 SOM uses U-BLOX’s NINA-B111 module. The module is based on Nordic’s nRF52832 BT SoC. The module main features are:

Bluetooth
Advanced Serial Port
GATT server and
Open CPU with Arm® Mbed™ and Nordic
External
Global

Please note The Silex M.2 module doesn’t support BT over UART.

MIPI CSI-2 CAMERA INTERFACE

The i.MX8 SOM supports a 4-Lanes MIPI CSI-2 interface. A 22 pins FPC connector on the SOM board enables a direct connection to a Camera supporting the CSI interface.

The connector pin-out is according to Allied Vision, a cameras manufacturer. The figure to the right describes the interface signals.

IMX-8 MIPI CSI channel
Implements all three CSI-2 MIPI layers
Scalable data lane support, 1 to 4 Data lanes
Supports high speed mode (80Mbps – 1.5Gbps) per lane, providing 4K@30fpscapability for the 4 lanes
Virtual Channel

i.MX8M SOM External Interfaces

General

The SOM incorporates three Hirose DF40 board-to-board headers. The selection of the Hirose DF40 is due to the following criteria:

Miniature (0.4m pitch)
Highly reliable manufacturer
Availability (worldwide distribution channels)
Excellent signal integrity (supports 6Gbps)
- Please contact Hirose or SolidRun for reliability and test result data.
Mating height of between 1.5mm to 4.0mm (1.5mm to 3.0mm if using 70-pin Board- to- Board header). SR-SOM-MX6 headers are fixed, the final mating height is determined by carrier implementation.

PCIe

The i.MX8 SOM supports two PCIe interfaces. The following figure describes the PCIe interfaces.

The PCIe main features are:

On board clock buffer sources all PCIe interfaces, on SOM and on Carrier
The IMX-8 CLK2_P/N clock output feeds the PCIe clock buffer
PCIe-1 can be used by the WI-FI module on the SOM or other module on the carrier. It is an assembly option.
5 / 2.5 / 3.0 / 5.0 / 6.0 Gbps Serializer / Deserializer.
Compliant with PCI Express Base Specification 2.1
Supports Spread Spectrum Clocking in Transmitter and Receiver
x1 Gen2
The PCIe TX signals are DC coupled by capacitors.
The clock are HSTL compatible, no decoupling capacitors.

USB 3.0

The i.MX8M supports two USB 3.0 interfaces. The following figure describes the USB interfaces.

The USB main features are:

USB 1 and USB 2 are directly connected to the connectors (No HUB).
The TX signals are DC coupled by capacitors.
Complies with USB specification rev 3.0 (xHCI compatible).
USB dual-role operation and can be configured as host or device.
Super-speed (5 Gbit/s), high-speed (480 Mbit/s), full-speed (12 Mbit/s), and low speed (1.5 Mbit/s) operations.
Supports four programmable, bidirectional USB endpoints.
OTG (on-the-go) 2.0 compliant, which includes both device and host capability. Super-speed operation is not supported when OTG is enabled.
The USB 3.0 module operates in following modes:
- Host Mode: SS/HS/FS/LS
- Device Mode: SS/HS/FS
- OTG: HS/FS/LS.
Power control signal are not part of the USB module, any available GPIO can be used.

MIPI CSI

The following figure describes the CSI interface.

MX8 MIPI CSI channel 1.
Implements all three CSI-2 MIPI layers.
Scalable data lane support, 1 to 4 Data lanes.
Supports high speed mode (80Mbps – 1.5Gbps) per lane, providing 4K@30fpscapability for the 4 lanes.
Virtual Channel

MIPI DSI

The following figure described the DSI interface.

The DSI main features are:

Implements all three DSI layers.
Support for Command and Video modes
Host Version
Scalable data lane support, 1 to 4 Data Lanes. (Optional bidirectional support on lane 0).
Support for all DSI data types and formats.
Virtual Channel
MIPI Alliance Specification for Display Serial Interface Version 1.1

Audio

The i.MX8M SOM supports up to three Audio channels, SAI1, SAI2 and SAI3. The following figure describes the audio interface.

The Audio main features are:

SAI1 supports 8TX and 8 RX channels.
SAI2 and SAI3 supports RX and TX
SPDIF Out.
Transmitter with independent bit clock and frame sync supporting 1 data line.
Receiver with independent bit clock and frame sync supporting 1 data line.
Each data line can support a maximum Frame size of 32 words.

For more details check the i.MX8M datasheet and AN.

Please note SAI1 signals are used as boot configuration during POR.

HDMI

The i.MX8M supports the HDMI interface including the signal termination. The following figure describes the HDMI interface :

The HDMI main features are:

On board pull-up termination to support HDMI levels.
HDMI HPD support 5V level.
HDMI DDC doesn’t support PU, need to support on carrier board.
Up to 4Kp60 video/graphics display over HDMI 2.0a with HDCP 2.2 encryption and audio formats including Dolby Digital, DTS, TrueHD,LPCM.

For more details check the i.MX8 datasheet.

Please note To support DPI, the pull-Up termination resistors are not assembled.

UART

The i.MX8 SOM can support up to 4 UART interfaces. The following figure describes the UART interfaces.

The UART interfaces main features are:

UART 1 supports TX and RX. Can be used as debug terminal.
UART 2 supports TX, RX, CTS and RTS. When using the RTS and CTS signals UART 4 is not available.
UART 3 Supports TX, RX, CTS and RTS.
UART 4 support TX and RX. It has an assembly options:
- On SOM BT module.
- Free UART on carrier board.
High-speed TIA/EIA-232-F compatible, up to Mbit/s.
9-bit or Multidrop mode (RS-485) support (automatic slave address detection).
7 or 8 data bits for RS-232 characters, or 9 bit RS-485 format.
Hardware flow control support for request to send (RTS_B) and clear to send (CTS_B) signals.
RS-485 driver direction control via CTS_B signal.
Auto baud rate detection (up to 115.2 Kbit/s).
DCE/DTE capability.

For more information check the i.MX8 datasheet.

eSPI

The i.MX8 SOM supports an eSPI interface. The following figure describes the eSPI interface.

MX8’s eSPI channel 2.
Single chip select nSS0.
Master/Slave configurable.
Polarity and phase of the Chip Select (SS) and SPI Clock (SCLK) are configurable.

Please note eSPI channel 1 is not available as default configuration. The signals supporting channel 1 are available as GPIO.

I2C

i.MX8 supports up to four I2c Interfaces. The following figure describes the I2C interfaces.

The I2C main features are:

I2C-1 is used only on the SOM. It is connected to the SOM EEPROM, PMIC and camera FPC connector.
I2C-2 and I2C-3 are available on the connector by default.
I2C-4 is not available as default configuration; it signals are available as GPIO.
Multimaster operation.
Software programmability for one of 64 different serial clock frequencies.
In Standard mode, I2C supports the data transfer rates up to 100 kbits/s.
In Fast mode, data transfer rates up to 400 kbits/s can be achieved.

MicroSD

The MicroSD supports the following features:

MX8 uSDHC-1.
Implements 4 data bits.
Support SD/SDIO standard, up to version 3.0.
Up to 400 Mbps of data transfer in SDR mode and up to 800 Mbps of data transfer in DDR mode using 4 parallel data lines.
8V or 3.3V support using SD2_VSELECT signal.