i.MX8M Plus SOM Hardware User Manual
Revisions and Notes
Date
Owner
Revision
Notes
08 Jan 2019
Noam Weidenfeld
1.0
12 Jun 2023
Noam Weidenfeld
1.1
02 Nov 2023
Shahar Fridman
1.2
Add Power Consumption Measurement
Introduction
This User Manual relates to the SolidRun i.MX8M-PLUS series , which includes;
Dual ARM A53 (1.8GHz)
Quad ARM A53 (1.8GHz)
SolidRun’s SR-SOM- i.MX8M family is a high-performance microsystem on module (S.O.M.) based on the highly integrated NXP i.MX8M family of products including the i.MX8M, i.MX8M-Mini and i.MX8M-Plus.
Highlighted Features
Ultra-small footprint SOM (47x30mm) including three board-to-board connectors (250 total pins number).
NXP i.MX8M-PLUS SoC (supports dual, quad lite and quad versions)
Up to quad Cortex A53 and up to 1.8GHz
Cortex-M7 subsystem processor supports real time tasks.
Neural Processing Unit (NPU) operating at up to 2.3 TOPS.
Dual Image Signal Processors and two camera inputs for an effective Vision System.
Video encode (including h.265) and decode, 3D/2D graphic acceleration, and multiple audio and voice functionalities.
Robust control networks supported by dual CAN FD and dual Gigabit Ethernet with Time-Sensitive Networking (TSN).
High industrial reliability with DRAM inline ECC and ECC on on-chip RAM.
LPDDR4 memory in x32 configurations supports up to 8GB and up to 4.0GT/s
Two Gigabit Ethernet interfaces based on Analog Device’s ADIN1300 chip.
Wi-Fi (802.11a/b/g/n/ac) + BT (5.0) Murata’s certified module (Cypress chipset)
On board MIPI-CSI interface supporting Basler’s camera’s modules.
On board LVDS connector supporting LCD and touch screen.
On board power and terminal interfaces supporting standalone operation.
Power management devices
Supporting Products
The following products are provided from SolidRun both as production level platforms and as reference examples on how to incorporate the SOM in different levels of integration:
Description
Block Diagram
The following figure describes the i.MX8M-PLUS Blocks Diagram.
Features Summary
Following are the features summary of the SOM. Notice that some of the features are pinout multiplexed (please refer to the pin mux table below and the NXP i.MX8M-PLUS data sheets):
NXP i.MX8M PLUS series SoC (Dual/Quad Lite/Quad ARM® Cortex™ A53 Processor, up to 1.8 GHz)
Cortex-M7 (800MHz) subsystem processor.
Up to 8GByte LPDDR4 memory and up to 4.0GT/s
Eight bits eMMC 5.1 memory.
I2C EEPROM.
HDMI 2.0a, 720 x 480p60, 1280 x 720p60, 1920 x 1080p60, 1920 x 1080p120 and 3840 x 2160p30
4-lanes MIPI-DSI interface
Two 4-Lanes LVDS interfaces (One of the interfaces support on-SOM connector for an LCD and touch screen)
Two 4-lanes MIPI CSI-2 (One of the interfaces is connected to an FPC connector supporting Basler’s MIPI cameras)
Two 10/100/1000 Mbps Ethernet PHY supporting 1588 standard
One Gigabit Ethernet controller with support for TSN
Wi-Fi (802.11a/b/g/n/ac) + BT (5.0) Murata’s certified module
Two USB 3.0 Host and Device
Single PCIe Gen 3 interfaces
Four bits SD interface
Single eSPI interface.
Single QSPI interface supporting up to 4 data bits
Up to three Synchronous Audio Interfaces.
Up to four Serial interfaces.
Up to 2 CAN-FD.
Power:
A single 5.0V input using B-t-B connector
A single 5.0V input using an On-SOM connector (Standalone operation)
3V output to support carrier’s digital interfaces
Core System Components
i.MX8M PLUS SoC Family
The i.MX 8M Plus family focuses on machine learning and vision, advanced multimedia, and industrial IoT with high reliability. It is built to meet the needs of Smart Home, Building, City and Industry 4.0 applications. The following figures show the functional modules in the i.MX 8M Plus processor system.
The following figures describes the i.MX8M-PLUS supported modules
Memory
The i.MX8M-PLUS SOM supports varieties of memory interfaces for booting and data storage. The following figure describes the IMX-8 SOM memory interfaces.
LPDDR4
Up to 8GB memory space.
32 Bits data bus.
Up to 4000 MT/s.
Supports D1, D2 and D4 die chips (Two CS).
Support various low power modes, clock and power gated operation.
Support Self-Refresh mode.
eMMC NAND Flash
Up to 64GB memory space.
8 Bits data bus.
Support MMC standard, up to version 5.1.
Up to 416 Mbps of data transfer for MMC cards using 8 parallel data lines in SDR mode.
Up to 3200 Mbps of data transfer for MMC cards using 8 parallel data lines in DDR mode.
uSDHC-3.
Can be used as BOOT NVM *
Quad Serial NOR Flash (SOM)
Each channel can be configured as 1/2/4-bit operation.
Support both SDR mode and DDR mode
No reset
QSPIA/nSS0.
Can be used as BOOT NVM *
EEPROM (SOM)
1Kb EEPROM
ON-Semi’s CAT24AA01TDI or compatible
I2C1
Address 0X50 (7 bits format)
Stores SOM’s configurations.
Micro-SD (Carrier)
Optional on Carrier board
IMX-8 uSDHC-1.
Implements 4 data bits.
Support SD/SDIO standard, up to version 3.0.
Up to 400 Mbps of data transfer in SDR mode and up to 800 Mbps of data transfer in DDR mode using 4 parallel data lines.
Can be used as BOOT NVM *
Serial NOR Flash (Carrier)
Optional on Carrier board
1 bits data bus.
eSPI2/nSS0
Can be used as BOOT NVM *
Please Note
(*) All boot configuration signals are available on the SOM connector.
10/100/1000 MBPS ETHERNET PHY
The SOM supports two Giga Ethernet interfaces. Both interfaces are connected to Analog Device’s ADIN1300 PHY.
Please note that default SOM configuration includes only 1 PHY. For 2nd PHY option please contact us for details.
RGMII interface.3 Ethernet interfaces for 1000BASE-T, 100BASE-TX, and10BASE-T.
Analog Device’s ADIN1300 PHY.
One Gigabit Ethernet controller with support for Energy Efficient Ethernet (EEE), Ethernet AVB, and IEEE 1588
One Gigabit Ethernet controller with support for TSN in addition to EEE, Ethernet AVB, and IEEE 1588.
WI-FI (11AC/B/G/N) BT (5.0 BLE)
The following figure describes the WI-FI and BT support in the i.MX8M-Plus SOM.
The WI-FI & BT module is Murata’s 1MW module Based on Cypress CYW43455. hip. The WI-FI main features are:
Operate at ISM frequency Band (2.4/ 5 GHz)
IEEE Standards Support 802.11ac, 802.11a, 802.11b, 802.11g and 802.11n
WI-FI over SDIO-1 interface
BT 5.0 BR/EDR/LE
BT over UART-1 Interface
Global certification.
MIPI-CSI
The i.MX8M-PLUS SOM supports a 4-Lanes MIPI CSI-2 interface. A 28 pins FPC connector on the SOM board enables a direct connection to Basler’s MIPI cameras. The following figure describes the interface signals.
CSI channel 2.
Implements all three CSI-2 MIPI layers.
Scalable data lane support, 1 to 4 Data Lanes.
When one camera is used, support up to 12MP@30fps or 4kp45.
When two cameras are used, each supports up to 1080p80.
Virtual Channel support.
Please note To connect CSI channel 2 to the ISP core, both ISPs need to be activated.
LVDS Interface
The i.MX8M-PLUS SOM supports a 4-Lanes LVDS interface. A 24 pins connector on the SOM board enables connection to a touch screen LCD. The following figure describes the interface signals.
LVDS channel 2.
LVDS Tx display and Pixel Mapper.
Up to 80MHz pixel clock and LVDS clock implying up to 560Mbps LVDS data rate (4 Lanes).
supports resolutions up to approximately 1366x768p60.
External Interfaces
General
The SOM incorporates three Hirose DF40 board-to-board headers.
The selection of the Hirose DF40 is due to the following criteria:
Miniature (0.4m pitch)
Highly reliable manufacturer
Availability (worldwide distribution channels)
Excellent signal integrity (supports 6Gbps)
Please contact Hirose or SolidRun for reliability and test result data.
Mating height of between 1.5mm to 4.0mm (1.5mm to 3.0mm if using 70-pin Board-to-Board header). SR-SOM-MX8M-PLUS headers are fixed, the final mating height is determined by carrier implementation
PCIe
The i.MX8M-PLUS SOM supports a single PCIe interfaces. The following figure describes the PCIe interfaces.
The PCIe main features are:
On board coupling capacitors for TX and CLK.
The i.MX8M-PLUS generates the PCIe clock.
PCI Express Base Specification 4.0 compliance.
2.5Gb/s, 5.0Gb/s, and 8.0Gb/s Serializer/Deserializer.
PHY Interface for the PCI Express Architecture, Version 4.2 compliance.
Supports Spread Spectrum Clocking in Transmitter and Receiver.
Receiver Detection.
Please note
The PCIe clock is generated in the i.MX8M-PLUS, check the datasheet if the jitter characteristics meet the application requirements.
USB 3.0
The i.MX8M-PLUS supports two USB 3.0 interfaces. The following figure describes the USB interfaces.
The USB main features are:
USB1 and USB2 are directly connected to the connectors (No HUB).
Complies with USB specification rev 3.0 (xHCI compatible).
USB dual-role operation and can be configured as host or device.
Super-speed (5 Gbit/s), high-speed (480 Mbit/s), full-speed (12 Mbit/s), and low speed (1.5 Mbit/s) operations.
Supports four programmable, bidirectional USB endpoints.
The USB 3.0 module operates in following modes:
Host Mode: SS/HS/FS/LS
Device Mode: SS/HS/FS
Power control signal are not part of the USB module, any available GPIO can be used.
Please note The voltage on VBUS is limited to 3.3V.
Please note There are no decupling capacitors on the SOM.
MIPI CSI
The following figure describes the CSI interface.
CSI channel 1.
Implements all three CSI-2 MIPI layers.
Scalable data lane support, 1 to 4 Data Lanes.
When one camera is used, support up to 12MP@30fps or 4kp45.
When two cameras are used, each supports up to 1080p80.
Virtual Channel support
ISP support
MIPI DSI
The following figure described the DSI interface.
The DSI main features are:
MIPI DSI Standard Specification V1.01r11.
Maximum resolution ranges up to WQHD (1920x1080p60, 24bpp).
Supports 1, 2, 3, or 4 data lanes.
Complies with Protocol-to-PHY Interface (PPI) in 1.0Gbps / 1.5Gbps MIPI DPHY.
Virtual Channel support.
Audio
The i.MX8M-PLUS SOM supports up to three Audio channels, SAI2, SAI3 and SAI5. It also supports an SPDIF interface. The following figure describes the audio interface.
The Audio main features are:
SAI2 and SAI3 supports RX and TX
SAI5 supports two RX channels
SPDIF input and output, including a raw capture input mode.
HiFi4 Audio DSP, operating up to 800 MHz
Supporting I2S, AC97, TDM, codec/DSP, and DSD interfaces.
All ports support 49.152 MHz BCLK.
8-channel PDM mic input.
Please note SAI1 signals are not directly output to the B-t-B connector. It can be used as an ALT function using other signals.
HDMI
The i.MX8M-PLUS supports HDMI interface. The following figure describes the HDMI interface.
The HDMI main features are:
On board Level translation for DDC channel and HDP signal.
HDMI 2.0a Tx supporting one display.
Resolutions of: 720 x 480p60, 1280 x 720p60, 1920 x 1080p60, 1920 x 1080p120,3840 x 2160p30.
32-channel audio output support.
UART
The i.MX8M-PLUS SOM can support up to 4 UART interfaces. The following figure describes the UART interfaces.
The UART interfaces main features are:
UART 1 is connected directly to the WI-FI/BT Modem to support the BT. It is available on the SOM B-t-B connector as an ALT function of SAI2.
UART 2 supports TX, RX and is used as terminal interface of the i.MX8M-PLUS. It is also available on J5002 when the SOM is operating in a standalone mode.
UART 3 Supports TX, RX, CTS and RTS.
UART 4 support TX and RX.
High-speed TIA/EIA-232-F compatible, up to Mbit/s.
9-bit or Multidrop mode (RS-485) support (automatic slave address detection).
RS-485 driver direction control via CTS_B signal.
Auto baud rate detection (up to 115.2 Kbit/s).
DCE/DTE capability.
Please note UART interfaces are available as ALT functional signals of other signals.
eSPI
The i.MX8M-PLUS SOM supports an eSPI interface. The following figure describes the eSPI interface.
IMX-8’s eSPI channel 2.
Single chip select nSS0.
Master/Slave configurable.
Please note eSPI channel 1 is not available as default configuration. The signals supporting channel 1 are available as GPIO.
I2C
The i.MX8M-PLUS supports up to four I2c Interfaces. The following figure describes the I2C interfaces.
The I2C main features are:
I2C-1 is used only on the SOM. It is connected to the SOM EEPROM and PMIC connector.
I2C-2 and I2C-3 are available on the connector by default.
I2C-4 is connected to the On-SOM FPC connector supporting Basler’s camera.
Multimaster operation.
In Standard mode, I2C supports the data transfer rates up to 100 kbits/s.
In Fast mode, data transfer rates up to 400 kbits/s can be achieved.
Please note I2C interfaces are available as ALT functional signals of other signals.
uSD
The uSD supports the following features:
IMX-8 uSDHC-1.
Implements 4 data bits.
Support SD/SDIO standard, up to version 3.0.
Up to 400 Mbps of data transfer in SDR mode and up to 800 Mbps of data transfer in DDR mode using 4 parallel data lines.
8V or 3.3V support integrated support.
Integrated power switch on SOM.
B2B Connector’s Signal Description
J5001
PIN
HBP 2.5
i.MX8M-PLUS 1.1
PIN
HBP 2.5
i.MX8M-PLUS 1.1
1
TP4
1V8
NC
2
NC
NC
3
DIP-SWITCH
1V8/ 3V3
BOOT_MODE0
1V8
4
DSI-CON (J19) or DSI-HDMI
DSI_DN3
5
DIP-SWITCH
1V8/ 3V3
BOOT_MODE1
1V8
6
DSI-CON (J19) or DSI-HDMI
DSI_DP3
7
GND
GND
8
GND
GND
9
DSI-CON (J19) or DSI-HDMI
DSI_CKP
10
GND
GND
11
DSI-CON (J19) or DSI-HDMI
DSI_CKN
12
DSI-CON (J19) or DSI-HDMI
DSI_DN0
13
GND
GND
14
DSI-CON (J19) or DSI-HDMI
DSI_DP0
15
DSI-CON (J19) or DSI-HDMI
DSI_DN2
16
GND
GND
17
DSI-CON (J19) or DSI-HDMI
DSI_DP2
18
Mini-PCIe (J20, optional)
LVDS0_CLK_P
19
GND
GND
20
Mini-PCIe (J20, optional)
LVDS0_CLK_N
21
DSI-CON (J19) or DSI-HDMI
DSI_DN1
22
GND
GND
27
M.2_WAKW_ON_LAN (PCIe)
NA
M.2_WAKW_ON_LAN,GPIO1.IO[12]
3V3
28
USB1_PWR_EN
3V3
USB1_PWR_EN, GPIO1.IO[15]
3V3
29
MIKROBUS (J10-4)
NA
UART3_TXD, GPIO5.IO[7]
3V3
30
GND
GND
31
MIKROBUS (J10-3)
NA
UART3_RXD, GPIO5.IO[6]
3V3
32
Mini-PCIe (J20, optional)
LVDS0_TX2_N
33
GND
GND
34
Mini-PCIe (J20, optional)
LVDS0_TX2_P
35
NC
NC
36
GND
GND
37
MIKROBUS (J10-1)
NA
UART3_CTS, GPIO5.IO[8]
3V3
38
Mini-PCIe (J20, optional)
LVDS0_TX3_N
41
HEADER, DIP-SW
3V3
SAI2_TXC, GPIO4.IO[25]
3V3
42
GND
GND
43
DSI_TS_nINT (DSI-HDMI)
3V3
SAI2_MCLK, GPIO4.IO[27]
3V3
44
LED (D34)
3V3
SAI2_RXC, GPIO4.IO[22] (UART1_RX)
3V3
45
NC
SAI2_TXD, GPIO4.IO[26]
3V3
46
LED (D33)
3V3
SAI2_RXFS, GPIO4.IO[21] (UART1_TX)
3V3
47
GND
GND
48
LED (D32)
3V3
SAI2_RXD, GPIO4.IO[23] (UART1_CTS)
3V3
49
NC
LVDS0_TX1_N
50
LED (D31)
3V3
SAI2_TXFS, GPIO4.IO[24] (UART1_RTS)
3V3
51
HEADER, DIP-SW
3V3
LVDS0_TX1_P
52
GND
GND
53
WIFI_DP (HUB to i.MX8M)
NA
LVDS0_TX0_N
54
CSI-CON(CON7)
CSI_DN0
55
WIFI_DN (HUB to i.MX8M)
NA
LVDS0_TX0_P
56
CSI-CON(CON7)
CSI_DP0
57
GND
GND
58
GND
GND
59
CSI-CON(CON7)
CSI_CKP
60
CSI-CON(CON7)
CSI_DP2
61
CSI-CON(CON7)
CSI_CKN
62
CSI-CON(CON7)
CSI_DN2
63
GND
GND
64
GND
GND
65
CSI-CON(CON7)
CSI_DP3
66
CSI-CON(CON7)
CSI_DP1
67
CSI-CON(CON7)
CSI_DN3
68
CSI-CON(CON7)
CSI_DN1
69
GND
GND
70
GND
GND
J7
PIN
HBP 2.5
i.MX8M-PLUS 1.0
PIN
HBP 2.5
i.MX8M-PLUS 1.0
1
ETH_NIC (Intel, U6)
PCIEC_CLKN
2
ETH_NIC (Intel, U6)
PCIE_RXN
3
ETH_NIC (Intel, U6)
PCIEC_CLKP
4
ETH_NIC (Intel, U6)
PCIE_RXP
5
GND
GND
6
GND
GND
7
ETH_NIC (Intel, U6)
PCIEC_TXN
8
HEADER (CON4)
NA
NC
9
ETH_NIC (Intel, U6)
PCIEC_TXP
10
mPCIe (J20)
3V3
Mini-PCIe_PREST#, GPIO1.IO[01]
3V3
11
GND
GND
12
HEADER (CON4)
NA
SPDIF_RX, GPIO5.IO[4]
3V3
13
M.2_RESET#
1V8
M.2_RESET#, GPIO1.IO[06]
3V3
14
POE_AT_DET
3V3
POE_AT_DET, GPIO1.IO[09]
3V3
15
RTC_CLKO (RTC Int.)
3V3
NC
16
DSI-CON (J19) or DSI-HDMI
NA
SPDIF_TX, GPIO5.IO[3]
3V3
17
GND
GND
18
M.2_PCIe_3V3_EN
3V3
M.2_PCIe_3V3_EN, GPIO1.IO[10]
3V3
19
HDMI CON (J1)
HDMI_TXP2
20
HEADER (CON4)
NA
SPDIF_EXT_CLK, GPIO5.IO[5]
3V3
21
HDMI CON (J1)
HDMI_TXN2
22
HEADER (CON4)
NA
NC
23
GND
GND
24
HEADER (CON4)
NA
DSI_EN, GPIO1.IO[08]
3V3
25
HDMI CON (J1)
HDMI_TXP1
26
USB-HUB_RST#
3V3
USB-HUB_RST#, GPIO1.IO[11]
3V3
27
HDMI CON (J1)
HDMI_TXN1
28
HEADER (CON4)
NA
QSPIA_DATA0, GPIO3.IO[6]
1V8
29
GND
GND
30
HEADER (CON4)
NA
QSPIA_DATA1, GPIO3.IO[7]
1V8
31
HDMI CON (J1)
HDMI_TXP0
32
TP6
QSPIA_DATA2, GPIO3.IO[8]
1V8
33
HDMI CON (J1)
HDMI_TXN0
34
NC
QSPIA_DATA3, GPIO3.IO[9]
1V8
35
GND
GND
36
HEADER (CON4)