> For the complete documentation index, see [llms.txt](https://dev.solid-run.com/llms.txt). Markdown versions of documentation pages are available by appending `.md` to page URLs; this page is available as [Markdown](https://dev.solid-run.com/nxp/imx6/sbc-platform/imx6-other-articles/add-support-for-i.mx6-solo-with-1gb-ddr.md). # Add support for i.MX6 Solo with 1GB DDR ### Overview The SolidRun i.MX6 Solo microSOM ships in two DRAM assemblies: * the standard **512MB** consumer assembly (2Gbit-density DDR3), and * a **1GB** assembly built from 4Gbit-density industrial memory modules. This page shows how to build U-Boot firmware that drives the **1GB** assembly, using the `CONFIG_MX6SOLO_1GB_DDR` build option in the `mx6cuboxi` board. {% hint style="info" %} **Applies to:** SolidRun i.MX6 Solo microSOM with 1GB DDR,[ SolidRun U-Boot tree](https://github.com/SolidRun/u-boot/tree/v2018.01-solidrun-imx6) (`v2018.01-solidrun-imx6` and equivalent branches), board target `mx6cuboxi`. {% endhint %} ## Revision and Notes | **Date** | **Owner** | **Revision** | **Notes** | | ---------- | --------- | ------------ | --------------- | | 9 Jun 2026 | Yazan | 1.0 | Initial release | ### How DRAM is configured During the SPL stage, the i.MX6 memory controller (MMDC) is initialized from a fixed configuration chosen by SoC type. Each variant pairs a calibration table (tuned to the SoM trace layout) with a chip-geometry description: ```c // board/solidrun/mx6cuboxi/mx6cuboxi.c — spl_dram_init() if (is_cpu_type(MXC_CPU_MX6D)) // Dual → 1GB mx6_dram_cfg(&sysinfo, &mx6q_1g_mmcd_calib, &mem_ddr_2g); else if (is_cpu_type(MXC_CPU_MX6Q)) // Quad → 2GB mx6_dram_cfg(&sysinfo, &mx6q_2g_mmcd_calib, &mem_ddr_4g); else if (is_cpu_type(MXC_CPU_MX6DL)) // DualLite → 1GB mx6_dram_cfg(&sysinfo, &mx6dl_1g_mmcd_calib, &mem_ddr_2g); else if (is_cpu_type(MXC_CPU_MX6SOLO)) // Solo → 512MB mx6_dram_cfg(&sysinfo, &mx6dl_512m_mmcd_calib, &mem_ddr_2g); ``` The Solo path uses the 512MB consumer geometry (`mem_ddr_2g`, a 2Gbit-density chip on a 32-bit bus). The 1GB assembly needs a different geometry: a **4Gbit-density** chip with a 15-bit row address. ### How the option works The 512MB and 1GB Solo SoMs share the **same PCB layout** — only the DRAM die density changes. Because the MMDC calibration (write-leveling, DQS gating, read/write delays) is governed by PCB trace lengths, the proven Solo calibration (`mx6dl_512m_mmcd_calib`) is reused, and only the chip geometry is swapped for the 4Gbit description. The selection is a compile-time option, `CONFIG_MX6SOLO_1GB_DDR`: * **Off (default):** firmware is identical to the standard build. * **On:** the Solo path is programmed for the 1GB assembly. #### Memory geometry `mem_ddr_solo_4g` describes a 4Gbit ×16 DDR3 device: | Field | Value | Meaning | | --------- | ----- | ---------------------------------- | | `density` | 4 | 4Gbit per device | | `width` | 16 | ×16 device | | `banks` | 8 | 8 banks | | `rowaddr` | 15 | 2¹⁵ rows (JEDEC value for 4Gb ×16) | | `coladdr` | 10 | 2¹⁰ columns | Per device: 2¹⁵ × 2¹⁰ × 8 × 16 bits = **4Gbit = 512MB**. On the Solo's 32-bit bus (two ×16 devices) → **1GB**. ### Source changes ```diff From: Jon Nettleton Subject: [PATCH] solidrun: mx6cuboxi: Add support for iMX6Solo 1GB The 1GB assembly for the MX6SOLO som is using 4Gb density industrial memory modules. This is different than our standard consumer grade assembly option. Add a kconfig option CONFIG_MX6SOLO_1GB_DDR to easily build a firmware to support this configuration of SOM. Signed-off-by: Jon Nettleton --- board/solidrun/mx6cuboxi/Kconfig | 4 ++++ board/solidrun/mx6cuboxi/mx6cuboxi.c | 19 +++++++++++++++++++ 2 files changed, 23 insertions(+) diff --git a/board/solidrun/mx6cuboxi/Kconfig b/board/solidrun/mx6cuboxi/Kconfig index 741c1754f8..c46820f177 100644 --- a/board/solidrun/mx6cuboxi/Kconfig +++ b/board/solidrun/mx6cuboxi/Kconfig @@ -9,4 +9,8 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "mx6cuboxi" +config MX6SOLO_1GB_DDR + bool "Enable alternative DDR configuration for the iMX6 SOLO SOM" + default n + endif diff --git a/board/solidrun/mx6cuboxi/mx6cuboxi.c b/board/solidrun/mx6cuboxi/mx6cuboxi.c index 8fad3febf9..e88216b450 100644 --- a/board/solidrun/mx6cuboxi/mx6cuboxi.c +++ b/board/solidrun/mx6cuboxi/mx6cuboxi.c @@ -949,6 +949,21 @@ static struct mx6_ddr3_cfg mem_ddr_2g = { .trasmin = 3500, }; +#if defined(CONFIG_MX6SOLO_1GB_DDR) +static struct mx6_ddr3_cfg mem_ddr_solo_4g = { + .mem_speed = 1600, + .density = 4, + .width = 16, + .banks = 8, + .rowaddr = 15, + .coladdr = 10, + .pagesz = 2, + .trcd = 1375, + .trcmin = 4875, + .trasmin = 3500, +}; +#endif + static struct mx6_ddr3_cfg mem_ddr_4g = { .mem_speed = 1600, .density = 4, @@ -1009,7 +1024,11 @@ static void spl_dram_init(int width) else if (is_cpu_type(MXC_CPU_MX6DL)) mx6_dram_cfg(&sysinfo, &mx6dl_1g_mmcd_calib, &mem_ddr_2g); else if (is_cpu_type(MXC_CPU_MX6SOLO)) +#if defined(CONFIG_MX6SOLO_1GB_DDR) + mx6_dram_cfg(&sysinfo, &mx6dl_512m_mmcd_calib, &mem_ddr_solo_4g); +#else mx6_dram_cfg(&sysinfo, &mx6dl_512m_mmcd_calib, &mem_ddr_2g); +#endif } void board_init_f(ulong dummy) ``` ### Build the firmware #### 1. Apply the patch ```bash git clone git@github.com:SolidRun/u-boot.git cd u-boot git checkout v2018.01-solidrun-imx6 git am 0001-solidrun-mx6cuboxi-Add-support-for-iMX6Solo-1GB.patch # or, for a plain patch file: # git apply --check 0001-...patch # dry-run # patch -p1 < 0001-...patch ``` #### 2. Enable `CONFIG_MX6SOLO_1GB_DDR` ```bash export ARCH=arm export CROSS_COMPILE=arm-linux-gnueabihf- echo 'CONFIG_MX6SOLO_1GB_DDR=y' >> configs/mx6cuboxi_defconfig make mx6cuboxi_defconfig make -j$(nproc) ``` #### 3. Flash ```bash # Adjust offsets to your boot device sudo dd if=SPL of=/dev/sdX bs=1k seek=1 conv=fsync sudo dd if=u-boot.img of=/dev/sdX bs=1k seek=69 conv=fsync ``` ### Verify On the U-Boot console, confirm the full 1GB is mapped and stable: ``` => bdinfo DRAM bank = 0x00000000 -> start = 0x10000000 -> size = 0x40000000 # 1024 MiB => mtest 0x10000000 0x4f000000 # stress the upper range; Ctrl-C to stop ``` Run a clean `mtest` (and, under Linux, `memtester 900M`) on the **1GB hardware** to confirm the reused calibration trains correctly on the industrial 4Gb parts. The 512MB and 1GB SoMs share the same PCB, so this is expected to pass — validate it once before shipping a production image. {% file src="/files/rJYoaaskm8hwGtucPZY1" %} {% file src="/files/ifVwIHcxkvemZdHrpSQI" %} {% file src="/files/JG3eGLPKqcMBaN9wQXwU" %} --- # Agent Instructions This documentation is published with GitBook. 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