i.MX6 SOM Hardware User Manual

Revision and Notes

Date	Owner	Revision	Notes
18 Jun 2014	Rabeeh Khoury	1.0	Initial release
24 Jul 2017	Rabeeh Khoury	1.1	Covers SOM rev 1.5 Documentation of booting from GPIOs
Nov 8, 2023	Shahar Fridman	1.2	Add power consumption table
12 Nov 2024	Yazan Shhady	1.3	Updated pin descriptions to include notes indicating where pins are unavailable on SOM version V1.9+.

Disclaimer No warranty of accuracy is given concerning the contents of the information contained in this publication. To the extent permitted by law no liability (including liability to any person by reason of negligence) will be accepted by SolidRun Ltd., its subsidiaries or employees for any direct or indirect loss or damage caused by omissions from or inaccuracies in this document. SolidRun Ltd. reserves the right to change details in this publication without prior notice. Product and company names herein may be the trademarks of their respective owners.

Introduction

This User Manual relates to the SolidRun SOM-i.MX6 series, which includes –

Single core ARM A9 (1 GHz) of the i.MX6 SoC: SOM-i1 (C1000S-D512-FE)

Dual lite core ARM A9 (1GHz) of the i.MX6 SoC: SOM-i2 (C1000DL-D1024-FE)

Dual core ARM A9 (1GHz) of the i.MX6 SoC: SOM-i2eX (C1000DM-D1024-GE-W)

Quad core ARM A9 (1GHz) of the i.MX6 SoC: SOM-i4 (C1000QM-D2048-GE-W)

Overview

The SolidRun SR-SOM-MX6 is a high performance micro system on module (SOM) based on the highly integrated NXP/Freescale i.MX6 family of products.

Highlighted Features

• Ultra small footprint SOM (47x30mm) including three board-to-board connectors. Mating height is carrier board dependent.
• Freescale i.MX6 SoC (supports solo, dual lite, dual and quad versions)

  • Up to quad Cortex A9 and up to 1.2GHz
  • Integrated multi format decoders and encoders, de-interlacing and color conversion functions
  • Integrated OpenVG, OpenGL ES 2.0 and OpenCL 1.1 EP GPU
  • DDR3 memories in x32 or x64 configurations (either 2 x16 or 4 x16 on a single chip select)
• Power management devices
• Gigabit Ethernet phy based on Qualcomm Atheros 8035 (footprint compatible with 8030 fast Ethernet phy)
• Rev 1.3 – Broadcom BCM4330 based WiFi 11n and Bluetooth 4.0 (2.4GHz)
• Rev 1.5 – TI Wilink8 based WiFi 11n (up to dual MIMO 2.4GHz/5GHz) and Bluetooth 4.1 / BLE

Supporting Products

The following products are provided from SolidRun both as production level platforms and as reference examples on how to incorporate the SOM in different levels of integration:

• HummingBoard (Base/Pro/Gate/Edge) – A board computer that incorporates the SOM retains the same Linux distributions while adding extra hardware functionalities and access to the hardware.
• CuBox-i – A minicomputer that is only 2″x2″x2″ in size that runs Linux with different distribution variants, use cases.

Summary of Features

Following is the features summary of the SOM. Notice that some of the features are pinout multiplexed (please refer to the pin muxing below and the Freescale i.MX6 data sheets):

• Freescale i.MX6 series SoC (Solo/Dual Lite/Dual/Quad ARM® Cortex™ A9 Processor, up to 1.2 GHz)
• Up to 2GByte
• HDMI 1.4 interface
• LVDS display interface
• MIPI DSI
• MIPI CSI-2
• Parallel camera interface
• Parallel display interface
• 10/100/1000 Mbps Ethernet PHY
• SOM rev 1.3 – Wireless LAN 802.11 b/g/n and Bluetooth 4.0
• SOM rev 1.5 – SISO or dual MIMO 2.4 or 5GHz (depends on part) 802.11 b/g/n with Bluetooth 4.1
• 1 x USB 2.0 host and 1 x USB 2.0 OTG
• 3 x SD / MMC interfaces
• Serial interfaces
• CAN Bus
• Required power supplies –

  • One 3.3V to 5.0V interface (called in the doc VIN_5V0)
  • One 3.3V (called in the doc NVCC_EIM0)
  • One SNVS and VDDHIGH_IN power supply (called in the doc VSNVS_3V0) Notice how NVCC_EIM0 and VSNVS_3V0 can be combined into one in the HummingBoard design.
  • Optionally two SD interface power supplies (NVCC_SD2, NVCC_SD3) can be externally set to either 3.3v or 1.8v for UHS-1 support.

Block Diagram

Core System Components

i.MX6 SOC Family

The Freescale i.MX6 SoC is an implementation of the ARM CortexTM-A9 core, which operates at frequencies up to 1.2 GHz. The i.MX6 provides a variety of interfaces and supports the following main features:

• Single, dual and quad processor ARM Cortex™-A9 SMP configuration. Each processor includes:

  • 32 Kbyte L1 Instruction Cache
  • 32 Kbyte L1 Data Cache
  • Private Timer and Watchdog
  • Cortex-A9 NEON MPE (Media Processing Engine) Co-processor:
  • SIMD Media Processing Architecture

    • NEON register file with 32×64-bit general-purpose registers
    • NEON Integer execute pipeline (ALU, Shift, MAC)
    • NEON dual, single-precision floating point execute pipeline (FADD, FMUL)
    • NEON load/store and permute pipeline
  • Unified L2 cache
  • General Interrupt Controller (GIC) with 128 interrupt support
  • Global Timer
  • Snoop Control Unit (SCU)
  • Integrated Power Management unit:

    • Die temperature sensor with alarms
    • Dynamic voltage and frequency scaling for low power modes
    • Flexible clock gating control scheme
  • Graphics, Multimedia & hardware acceleration engines:

    • Video Processing Unit (VPU) – A DSP with hardware acceleration engines for video decoding and encoding
    • Image Processing Unit (IPUv3) – A hardware engine for processing images, frames, de-interlacing and various other tasks
    • 3D Graphics Processing Engine (3D GPU) – OpenGL ES 2.0 and OpenCL 1.1 EP GPU engine scalable from one shader up to 4
    • 2D Graphics Processing Engine (2D GPU) – For BitBlt function etc…
    • 2D Graphics Processing Engine (OpenVG) – OpenVG compliant GPU
    • Asynchronous sample rate converters (ASRC)
  • Security:

    • ARM TrustZone including the TZ architecture (interrupt and memory separation)
    • CAAM module – cipher acceleration and assurance module including a true pseudo random number generator (NIST certified)
    • Secure boot (HAB) and central security unit controlled via OTP fuses
  • I/O:

    • High Speed USB 2.0 OTG (Up to 480 Mbps) with integrated HS USB Phy
    • High Speed USB 2.0 HOST (Up to 480Mbps) with integrated USB phy
    • Single lane PCI-Express 2.0 (includes clock generation)
    • Misc. SD and MMC interface with 3.3v / 1.8v voltage level support (for UHS-1 speeds)
  • Misc. serial interfaces (SPI, NOR, I2S, I2C, CAN etc…)

Please refer to Freescale i.MX6 datasheets with regards to differences between the various devices, number of processors, L2 cache size, GPU supported (i.e. gc880 vs gc2000), etc…

10/100/1000 MBPS Ethernet PHY

The Ethernet PHY is based on the Qualcomm / Atheros AR8035 PHY and incorporates the following features:

• 10BASE-Te/100BASE-TX/1000BASE-T IEEE 802.3 compliant
• 1000BASE-T PCS and auto-negotiation with next page support
• IEEE 802.3az EEE
• Green ETHOS power saving modes with internal automatic DSP power-saving scheme
• SmartEEE
• Wake on LAN
• Automatic MDI/MDIX crossover and polarity correction
• IEEE 802.3u compliant auto negotiation
• Cable Diagnostic Test (CDT)

The PHY is connected via the i.MX6 RGMII interface.

BCM 4330 Based (SOM Rev 1.3) – Wireless LAN 802.11 B/G/N & Bluetooth 4.0 SiP

The system in package (SiP) is based on the AzureWave AW-NH660 module and incorporates the following features:

• BCM4330 WiFi / BT based
• WiFi / BT co-existence support
• WiFi :

  • Integrated CPU with on-chip memory for complete WLAN subsystem minimizing the need to wake up the application processor
  • SDIO based interface (connected via the i.MX6 SD1 interface)
  • Single band 2.4 GHz 802.11 b/g/n
  • Supports IEEE 802.11d, e, j, I, j, r, k, w
  • WEP, WPA/WPA2, AES, TKIP, CKIP (SW) based security
  • WMM/WMM-PS/WMM-SA
  • Proprietary protocols – CCXv2/CCXv3/CCXv4/CCXv5, WFAEC
• Bluetooth:

  • Fully supports Bluetooth 4.0 + EDR (AFH, QoS, eSCO, fast connect, SSP, SSR, EPR, EIR, LST)
  • High speed UART (max 4Mbps) and PCM for Bluetooth support (connected via i.MX6 UART4 interface and i.MX6 AUD3 audio PCM interface)
  • HS packet types, class 1 or class 2 transmitter type operation

TI WiLink8 Based(SOM Rev 1.5) – Wireless LAN 802.11 B/G/N & Bluetooth 4.1 SiP

The SiP (System in package) incorporates the following features –

• TI Wilink 8 WiFi / BT based
• WiFi / BT co-existence support
• WiFi :

  • Integrated RF front end, power amplified, DC-DC, crystal, switches, filters and power management
  • SDIO based interface (connected via the i.MX6 SD1 interface)
  • 2.4 GHz or 5 GHz (depending on model) 802.11 a/b/g/n
  • SISO or MIMO (two antennas)
  • 20 and 40 MHz channels on 2.4/5 GHz bands
  • Wi-Fi direct multi-role multi-channel
  • Up to 10 clients supported in AP role
• Bluetooth:

  • Fully supports Bluetooth 4.1 + EDR including Bluetooth low energy
  • High speed UART (max 4Mbps) and PCM for Bluetooth support (connected via i.MX6 UART4 interface

i.MX6 SOM Interfaces

i.MX6 SOM- External Interfaces Brief

The SOM incorporates three Hirose DF40 board-to-board headers. The selection of the Hirose DF40 is due to the following criteria:

• Miniature (0.4m pitch)
• Highly reliable manufacturer
• Availability (worldwide distribution channels)
• Excellent signal integrity (supports 6Gbps)

  • Please contact Hirose or SolidRun for reliability and test result data.
• Mating height of between 1.5mm to 4.0mm (1.5mm to 3.0mm if using 70-pin Board-to-Board header). SR-SOM-MX6 headers are fixed, the final mating height is determined by carrier implementation

The different board-to-board functionality is defined as follows:

• Main 80 pin B2B. Includes the following functionality:

  • Main supply +3.3v to +5.0v in (5 pins)
  • I/O supply +3.3V and SD2, SD3 supplies (can be fixed +3.3V or externally switched +3.3V / 1.8V to support UHS-1)
  • Ethernet MDI (4 differential pairs), LED activity or link (10/100/1000) and Ethernet TCT
  • SATA TX/RX (2 differential pairs) – Functional on i.MX6 dual and quad (not supported on solo / dual lite)
  • USB OTG and HOST (2 differential pairs)
  • Various GPIOs and pins that can be muxed. By default, it is configured to be 2xI2C, PWMs (1 through 4), SPI 2, SD2 interface and USB enable.
• Second 80 pin B2B. The board-to-board exposes the following functionality:

  • System power on reset
  • HDMI 1.4 (4 differential pairs), CEC, +5V boosted I2C and HDMI HPD
  • PCI express 2.0 (3 differential pairs include TX/RX and clock)
  • USB OTG charge detect and USB OTG ID
  • MIPI CSI 2 (3 differential pairs for solo / dual lite and 5 differential pairs for dual / quad versions)
  • MIPI DSI (3 differential pairs)
  • LVDS 0 (5 differential pairs)
  • UART1 (typically used for main system debug port)
  • Various GPIOs and pins that can be muxed. By default, it is configured to be AUD5 I2S interface, CCM CLKO1/CLKO2, SD2 voltage select, SPDIF out, USB HOST / OTG over current indication.
• Third 70 pin B2B. This board-to-board exposes the following functionality:

  • Power management (EIM_WAIT, TAMPER, PMIC standby, MX6_ONOFF, PMIC_ON_REQ)
  • Boot mode override
  • MLB interface (marked as reserved on rev 1.3 and not available on rev 1.5. Contact SolidRun about availability of i.MX6 SOM with MLB interface)
  • Various GPIOs and pins that can be muxed. By default it is configured to be UART3, SPDIF in, Display and camera parallel interface, UART2, Watchdog timer, SD3 and SD4 interfaces)

SR-SOM-MX6 ON Board Functions

10/100/1000 Mbps PHY

The SOM incorporates a Qualcomm / Atheros AR8035 PHY. The PHY connectivity is as follows:

• Uses 2.5V interface voltage level
• RGMII (optional AR8030 with RMII)
• Phy reset function via i.MX6 pad V5 (KEY_ROW4). Active low
• Default phy address either 0x0 or 0x4 (depends on LED activity reset strap, either pulled down or pulled up)

Please note Note that due to internal i.MX6 buses the 1000Mbps interface speed is limited to 470Mbps.

802.11 b/g/n and Bluetooth SiP

The SOM incorporates AzureWave AW-660 SiP or TI Wilink8 SiP. The SiP interfaces are:

• WiFi connectivity via i.MX6 SDIO1
• Bluetooth connectivity via i.MX6 UART4
• Audio PCM connectivity via i.MX6 AUD3
• Antenna via onboard UFL connector

i.MX6 SOM External Interfaces Detailed Description

As previously described, the SOM incorporates three Hirose DF40 based board-to-board headers.

The SOM uses the header of these board-to-board connectors which is fixed in height, while the mating height is determined by the carrier, by using different Hirose DF40 receptacle mating heights (1.5 to 4.0mm) (1.5mm to 3.0mm if using 70-pin Board-to-Board header).

J5002 Board to Board Header Pin Description

This board-to-board header uses Hirose DF40 DH40C-80DP-0.4V(51) header. The pin description may be found in the following tables:

Notes	IC ball number	IC pad name	Driving IC	Schematics pad	Pin number	Pin number	Schematics pad	Driving IC	IC pad name	IC ball number	Notes
				GND	2	1	MDI_TRXN3	Ethernet PHY	MDI_TRXN3	19	Diff 100 Ohm
Diff 100 Ohm	B14	SATA_RXP	i.MX6	SATA_RXP	4	3	MDI_TRXP3	Ethernet PHY	MDI_TRXP3	18	Diff 100 Ohm
Diff 100 Ohm	A14	SATA_RXM	i.MX6	SATA_RXN	6	5	GND
				GND	8	7	MDI_TRXN2	Ethernet PHY	MDI_TRXN2	16	Diff 100 Ohm
Diff 100 Ohm	B12	SATA_TXM	i.MX6	SATA_TXN	10	9	MDI_TRXP2	Ethernet PHY	MDI_TRXP2	15	Diff 100 Ohm
Diff 100 Ohm	A12	SATA_TXP	i.MX6	SATA_TXP	12	11	GND
				GND	14	13	MDI_TRXN1	Ethernet PHY	MDI_TRXN1	13	Diff 100 Ohm
Diff 90 Ohm	A6	USB_OTG_DP	i.MX6	USB_OTG_DP	16	15	MDI_TRXP1	Ethernet PHY	MDI_TRXP1	12	Diff 100 Ohm
Diff 90 Ohm	B6	USB_OTG_DN	i.MX6	USB_OTG_DN	18	17	GND
				GND	20	19	MDI_TRXN0	Ethernet PHY	MDI_TRXN0	10	Diff 100 Ohm
Diff 90 Ohm	E10	USB_H1_DP	i.MX6	USB_HOST_DP	22	21	MDI_TRXP0	Ethernet PHY	MDI_TRXP0	9	Diff 100 Ohm
Diff 90 Ohm	F10	USB_H1_DN	i.MX6	USB_HOST_DN	24	23	GND
				GND	26	25	LED_10_100_1000	Ethernet PHY	LED_10_100_1000	22
	T5	GPIO_0	i.MX6	USB_H1_PWR_EN	28	27	LED_ACT	Ethernet PHY	LED_ACT	21
	E23	EIM_D22	i.MX6	USB_OTG_PWR_EN	30	29	ETH_TCT	Ethernet PHY	ETH_TCT	N/A
BOOT_CFG4[5]	K20	EIM_RW	i.MX6	ECSPI2_SS0	32	31	I2C3_SCL	i.MX6	EIM_D17	F21	4.7kohm NVCC_EIM0 pulled up
BOOT_CFG4[2]	K22	EIM_LBA	i.MX6	ECSPI2_SS1	34	33	I2C3_SDA	i.MX6	EIM_D18	D24	4.7kohm NVCC_EIM0 pulled up
				GND	36	35	GND
	C21	SD2_CLK	i.MX6	SD2_CLK	38	37	SD3_CLK	i.MX6	SD3_CLK	D14	This signal is not available on SOM V1.9+ with or without eMMC, or on SOM V1.5 with eMMC.
	F19	SD2_CMD	i.MX6	SD2_CMD	40	39	SD3_CMD	i.MX6	SD3_CMD	B13	This signal is not available on SOM V1.9+ with or without eMMC, or on SOM V1.5 with eMMC.
	A22	SD2_DATA0	i.MX6	SD2_DATA0	42	41	PWM2_OUT	i.MX6	DISP0_DAT9	T25
	E20	SD2_DATA1	i.MX6	SD2_DATA1	44	43	USB_OTG_VBUS	i.MX6	USB_OTG_VBUS	E9
	A23	SD2_DATA2	i.MX6	SD2_DATA2	46	45	ECSPI2_MISO	i.MX6	EIM_OE	J24
	B22	SD2_DATA3	i.MX6	SD2_DATA3	48	47	ECSPI2_MOSI	i.MX6	EIM_CS1	J23
	R6	GPIO_4	i.MX6	SD2_CD_B	50	49	ECSPI2_SCLK	i.MX6	EIM_CS0	H24
	D10	USB_H1_VBUS	i.MX6	USB_H1_VBUS	52	51	I2C1_SDA	i.MX6	EIM_D28	G23	4.7kohm NVCC_EIM0 pulled up
BOOT_CFG1[6]	K25	EIM_DA6	i.MX6	DISP1_DATA03	54	53	I2C1_SCL	i.MX6	EIM_D21	H20	4.7kohm NVCC_EIM0 pulled up
BOOT_CFG1[7]	L25	EIM_DA7	i.MX6	DISP1_DATA02	56	55	PWM3_OUT	i.MX6	SD4_DAT1	B19
BOOT_CFG1[3]	K24	EIM_DA3	i.MX6	DISP1_DATA06	58	57	PWM4_OUT	i.MX6	SD4_DAT2	F17
BOOT_CFG2[0]	L24	EIM_DA8	i.MX6	DISP1_DATA01	60	59	__NC__SPDIF_CLK_IN	NC
BOOT_CFG1[4]	L22	EIM_DA4	i.MX6	DISP1_DATA05	62	61	NVCC_SD2	i.MX6	NVCC_SD2	G17
BOOT_CFG1[5]	L23	EIM_DA5	i.MX6	DISP1_DATA04	64	63	NVCC_SD3	i.MX6	NVCC_SD3	G14
BOOT_CFG2[1]	M21	EIM_DA9	i.MX6	DISP1_DATA00	66	65	NVCC_EIM0	Many			Although called NVCC_EIM0, this power rail supplies the i.MX6, Ethernet phy, WiFi / BT and others. Refer to the public schematics for more details.
	R22	DISP0_DAT8	i.MX6	PWM1_OUT	68	67	NVCC_EIM0
				GND	70	69	VSNVS_3V0	i.MX6			In rev 1.2 and beyond this is VDD_SNVS_IN and VDDHIGH_IN power domains
				GND	72	71	VIN_5V0
				GND	74	73	VIN_5V0
				GND	76	75	VIN_5V0
				GND	78	77	VIN_5V0
				GND	80	79	VIN_5V0

J8004 Board to Board Header Pin Description

Notes	IC ball number	IC pad name	Driving IC	Schematics pad	Pin number	Pin number	Schematics pad	Driving IC	IC pad name	IC ball number	Notes
Diff 85 Ohm	B1	PCIE_RXM	i.MX6	PCIE_RXM	2	1	CLK1_P	i.MX6	CLK1_P	D7	Diff 85 Ohm
Diff 85 Ohm	B2	PCIE_RXP	i.MX6	PCIE_RXP	4	3	CLK1_N	i.MX6	CLK1_N	C7	Diff 85 Ohm
				GND	6	5	GND
Diff 100 Ohm	E4	CSI_D0M	i.MX6	CSI_D0M	8	7	PCIE_TXM	i.MX6	PCIE_TXM	A3	Diff 85 Ohm
Diff 100 Ohm	E3	CSI_D0P	i.MX6	CSI_D0P	10	9	PCIE_TXP	i.MX6	PCIE_TXP	B3	Diff 85 Ohm
				GND	12	11	GND
Diff 100 Ohm	D1	CSI_D1M	i.MX6	CSI_D1M	14	13	CSI_CLK0P	i.MX6	CSI_CLK0M	F3	Diff 100 Ohm
Diff 100 Ohm	D2	CSI_D1P	i.MX6	CSI_D1P	16