CN9132 COM Hardware User Manual

Dual Revision and Notes

Date	Owner	Revision	Notes
26 Apr 2020	Alon Rotman	1.0	1. Initial release information 2. Relevant for PCB revision 1.0
10 Oct 2020	Alon Rotman	1.1	1. Update CN913x configurations 2. Update Connector A/B C/D pinout 3. Relevant for PCB rev1.1
29 Oct 2020	Alon Rotman	1.2	Updated CP[2:0] MPPs tables according to PCB rev1.1
Dec 01, 2024	Josua Mayer	1.3	Cosmetic updates and minor corrections to MPP and connector tables according to PCB rev1.3
Dec 30, 2024	Josua Mayer	1.3.1	Marked PTP feature as Untested.

Disclaimer No warranty of accuracy is given concerning the contents of the information contained in this publication. To the extent permitted by law no liability (including liability to any person by reason of negligence) will be accepted by SolidRun Ltd., its subsidiaries or employees for any direct or indirect loss or damage caused by omissions from or inaccuracies in this document. SolidRun Ltd. reserves the right to change details in this publication without prior notice. Product and company names herein may be the trademarks of their respective owners.

Introduction

This document is intended for hardware engineers that are willing to integrate CN913x COM express type 7 module from SolidRun ltd.

The document provides details with regards CN913x module rev 1.3.

Overview

• CN9132 COM Express type 7 is a highly integrated COM modules based on Marvell’s CN913x SoC.
• The SoC highlights are up to 2.2GHz with 4 Cortex A72 Arm cores, DDR4 controller and 18 high speed SERDESs.

The module integrates the following features –

1. CN9130 SoC (up to 2.2GHz).
2. SO-DIMM DDR4 connected to the DDR controller. The SO-DIMM supports up to 16GByte SO-DIMM DDR4 2400Mtps memory with and without ECC, registered or non-registered.
3. Single 12V DC-input is required.

Specifications

Features	CN9132	CN9131	CN9130
Form Factor	COM Express type 7	COM Express type 7	COM Express type 7
Processor Core	4 cores Arm Cortex A72	4 cores Arm Cortex A72	4 cores Arm Cortex A72
Processor speed	Up to 2.2GHz	Up to 2.2GHz	Up to 2.2GHz
Memory	Dual Channel SO-DIMM DDR4; up to 32GB at 2400MT/s (16GB for each channel)	Dual Channel SO-DIMM DDR4; up to 32GB at 2400MT/s (16GB for each channel)	Dual Channel SO-DIMM DDR4; up to 32GB at 2400MT/s (16GB for each channel)
ECC	Optional	Optional	Optional
eMMC	Up to 64GB (assembled 8GB)	Up to 64GB (assembled 8GB)	Up to 64GB (assembled 8GB)
Flash	64Mbit SPI NOR flash	64Mbit SPI NOR flash	64Mbit SPI NOR flash
SATA 3.0	2	1	0
Supported OS	Linux kernel 5.8x Yocto DPDK UEFI KVM/QEMU/Containers NFV Openstack compute node	Linux kernel 5.8x Yocto DPDK UEFI KVM/QEMU/Containers NFV Openstack compute node	Linux kernel 5.8x Yocto DPDK UEFI KVM/QEMU/Containers NFV Openstack compute node
XFI/RXAUI/SGMII	3	2	1
PCIe gen 3.0	1 x PCIe Gen 3.0 x4 1 x PCIe Gen 3.0 x2 6 x PCIe Gen 3.0 x1	1 x PCIe Gen 3.0 x4 1 x PCIe Gen 3.0 x2 3 x PCIe Gen 3.0 x1	1 x PCIe Gen 3.0 x4 1 x PCIe Gen 3.0 x1
USB 3.0	1	0	0
I2C	6	5	4
SMI & XSMI	3	2	1
UART	2	2	2
PPS/PTP/Sync-E support	Untested, for authoritative information, consult Marvell documentation and Errata (available under NDA).	Untested, for authoritative information, consult Marvell documentation and Errata (available under NDA).	Untested, for authoritative information, consult Marvell documentation and Errata (available under NDA).
SPI bus	✓	✓	✓
RTC support	✓	✓	✓
Power	12V (9V-15V) up to 15W full system	12V (9V-15V) up to 13W full system	12V (9V-15V) up to 11W full system
Environment	Commercial: 0°C to 70°C Industrial: -40°C to 85°C Humidity (non-condensing): 10% – 90%	Commercial: 0°C to 70°C Industrial: -40°C to 85°C Humidity (non-condensing): 10% – 90%	Commercial: 0°C to 70°C Industrial: -40°C to 85°C Humidity (non-condensing): 10% – 90%
Dimensions	125mm X 95mm	125mm X 95mm	125mm X 95mm

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Simplified Schematics

CN9130 COM express type 7 simplified schematics is intended for the following audience –

1. Software and firmware engineers that enables them to understand the IO and signal connectivity of the COM express design.
2. Hardware engineers that are willing to use the COM express and build their own development board. This document completes the CEx7 CN9130 reference manual from description of signal and implementation wise.

Power Consumption

TBD

High Speed port configuration

The CN9130 Com Express Type 7 family includes 3 variations:

1. CN9130 is comprised from a single CN9130.
2. CN9131 is comprised from a single CN9130 with one additional 88F8215. This includes a CP with 6 shared high speed SERDES interfaces, for a total of 12 lanes.
3. CN9132 is comprised from a single CN9130 with two additional 88F8215. Each one of them has a CP with 6 shared high speed SERDES interfaces, for a total of 18 lanes.

Maximum Port combination:

Feature	CN9132	CN9131	CN9130
PCIe 3.0	1x Port X4 lanes + 2x Ports X1 Total of 3 controllers and up to 6 lanes	1x Port X4 lanes + 2x Ports X1 Total of 3 controllers and up to 6 lanes	1x Port X4 lanes + 2x Ports X1 Total of 3 controllers and up to 6 lanes
Ethernet	3x 10/5 GbE port + 6x 1/2.5 GbE Ports or 6x 5 GbE Port + 3x 1/2.5 GbE Port	2x 10/5 GbE port + 4x 1/2.5 GbE Ports or 4x 5 GbE Port + 2x 1/2.5 GbE Port	1x 10/5 GbE port + 2x 1/2.5 GbE Ports or 2x 5 GbE Port + 1x 1/2.5 GbE Port
USB 3.0	6 x USB 3.0 (Host/Device)	4 x USB 3.0 (Host/Device)	2 x USB 3.0 (Host/Device)
SATA 3.0	6 x SATA 3.0	4 x SATA 3.0	2 x SATA 3.0
SERDES LANES	18 Lanes	12 Lanes	6 Lanes
88F8215	2	1	0

SERDES MUXing

Each CP (CP0, CP1 and CP2) support the same mux options individually:

Interface	SERDES Lane0	SERDES Lane1	SERDES Lane2	SERDES Lane3	SERDES Lane4	SERDES Lane5
10GBASE-R/XFI			Port 0		Port 0
5GBASE-R			Port 0		Port 0 or 1
10GBASE-X2 (RXAUI)			Port 0 Lane 0	Port 0 Lane 1	Port 0 Lane0	Port 0 Lane 1
1000BASE-X (SGMII) / 2.5GBASE-X (HS-SGMII)	Port 1	Port 2	Port 0	Port 1	Port 0 or 1	Port 2
SATA 3.0	Port 1	Port 0	Port 0	Port 1		Port 1
USB 3.0 HOST		Port 0	Port 0	Port 1	Port 1
USB 3.0 Device		Port 0			Port0
PCIe RC/EP	PCIex4 Port0 LANE0	PCIex4 Port0 LANE1	PCIex4 Port0 LANE2	PCIex4 Port0 LANE3	PCIex1 Port1	PCIex1 Port2
Evaluation Board Default Configuration of CP0	PCIex4 Port 0 Lane 0	PCIex4 Port 0 Lane 1	PCIex4 Port 0 Lane 2	PCIex4 Port 0 Lane 3	10GBASE-R/XFI Port 0	2.5GBASE-X/HS-SGMII Port 2
Evaluation Board Default Configuration of CP1	PCIex2 Port0 LANE0	PCIex2 Port0 LANE1	10GBASE-R/XFI Port 0	SATA 3.0 Port 1	PCIex1 Port 1	PCIex1 Port 2
Evaluation Board Default Configuration of CP2	PCIex1 Port 0	USB-3.0 Host Port 0	5GBASE-R/XFI Port 0	SATA 3.0 Port 1	PCIex1 Port 1	PCIex1 Port 2

The following port configurations can’t be used simultaneously:

• SGMII port 0 / HS SGMII port0, RXAUI and XFI/10GBASE
• SGMII port 1 and HS SGMII port 1
• SGMII port 2 and HS SGMII port 2

Note that all PCIe lanes specified in the CN9132 default configuration are connected to PCIe pins in the COM Express connector and are routed as 90 ohm differential pairs

AP/CP[0:2] Multi Purpose Pins

AP MPP[0:19]

MPP #	Pin #	Pin Description	Notes
AP_MPP[0]	AP10	AP_SD_CLK	1.8V, serial 22ohm resistor
AP_MPP[1]	AT10	AP_SD_CMD	1.8V, 10K PU
AP_MPP[2]	AP16	AP_SD_D[0]	1.8V, 10K PU
AP_MPP[3]	AP18	AP_SD_D[1]	1.8V, 10K PU
AP_MPP[4]	AT16	AP_SD_D[2]	1.8V, 10K PU
AP_MPP[5]	AP14	AP_SD_D[3]	1.8V, 10K PU
AP_MPP[6]	AP12	AP_SD_DS	RCLK, 10K PD
AP_MPP[7]	AT14	AP_SD_D[4]	1.8V, 10K PU
AP_MPP[8]	AT12	AP_SD_D[5]	1.8V, 10K PU
AP_MPP[9]	AT18	AP_SD_D[6]	1.8V, 10K PU
AP_MPP[10]	AV18	AP_SD_D[7]	1.8V, 10K PU
AP_MPP[11]	AY18	AP_UA0_TXD	PD - Reset strap 3.3V through FXL2TD245L10X level shifter
AP_MPP[12]	BA17	AP_SD_HW_RST	1.8V, 10K PD
AP_MPP[19]	AW17	AP_UA0_RXD	3.3V through FXL2TD245L10X level shifter

CP0 MPP[0:62]

MPP #	Pin #	Pin Description	Notes
MPP[0]	AY38	CP_GE1_RXD[3]
MPP[1]	AV38	CP_GE1_RXD[2]
MPP[2]	AW39	CP_GE1_RXD[1]
MPP[3]	AY40	CP_GE1_RXD[0]
MPP[4]	AW41	CP_GE1_RXCTL
MPP[5]	BA39	CP_GE1_RXCLK
MPP[6]	AW35	CP_GE1_TXD[3]
MPP[7]	AY36	CP_GE1_TXD[2]
MPP[8]	BA37	CP_GE1_TXD[1]
MPP[9]	AW37	CP_GE1_TXD[0]
MPP[10]	BA35	CP_GE1_TXCTL
MPP[11]	AV36	CP_GE1_TXCLKOUT
MPP[12]	AV32	CP_SPI1_CSn[1]	3.3V
MPP[13]	AY34	CP_SPI1_MISO	3.3V
MPP[14]	AT36	CP_SPI1_CSn[0]	3.3V, for on-SoM SPI Flash
MPP[15]	AT32	CP_SPI1_MOSI	3.3V, 10k PD, CPU Subsystem Clock CP0_SYS_PLL_SEL0
MPP[16]	AV34	CP_SPI1_SCK	3.3V, 10k PU, 1k PD via SW2-1, CPU Subsystem Clock CP0_SYS_PLL_SEL1
MPP[17]	BA29	CP_GPIO[17]	3.3V, 10k PU, 1k PD via SW2-2, CPU Subsystem Clock CP0_SYS_PLL_SEL2
MPP[18]	AW29	CP_BOOT_MODE_SEL0	3.3V, 10k PU, 4.7k PD via SW1-5, Boot Mode[0]
MPP[19]	AV30	CP_BOOT_MODE_SEL1	3.3V, 10k PU, 4.7k PD via SW1-4, Boot Mode[1]
MPP[20]	BA31	CP_BOOT_MODE_SEL2	3.3V, 10k PU, 4.7k PD via SW1-3, Boot Mode[2]
MPP[21]	AT30	CP_BOOT_MODE_SEL3	3.3V, 10k PU, 1k PD via SW1-2, Boot Mode[3]
MPP[22]	AY30	CP_BOOT_MODE_SEL4	3.3V, 10k PU, 4.7k PD via SW1-1, Boot Mode[4]
MPP[23]	AP32	CP_BOOT_MODE_SEL5	3.3V, 10k PU, Boot Mode[5]
MPP[24]	AP34	CP_MPP[24]	3.3V, 2.2K PU
MPP[25]	AT34	CP_MPP[25]	3.3V, 2.2k PD, Reset strap
MPP[26]	AT38	CP_MPP[26]	3.3V, 10k PU, Reset strap
MPP[27]	AW31	CP_MPP[27]	3.3V, 10K PU, SODIMM EVENT_N
MPP[28]	AY32	CP_PTP_PULSE
MPP[29]	BA33	CP_PTP_CLK
MPP[30]	AW33	CP_PTP_PCLK_OUT
MPP[31]	AP36	CP_MPP[31]	3.3V, 2.2K PU, PWRBTN_N
MPP[32]	H30	CP_MPP[32]	BIOS_DIS status
MPP[33]	C39	CP_MPP[33]	BIOS_DIS override BIOS_DIS
MPP[34]	C41	CP_MPP[34]	3.3V, 2.2K PU, SUS_5_N
MPP[35]	F32	CP_I2C1_SDA	3.3V, 2.2K PU, i2c mux, used addresses: 0x53, 0x2F, 0x6A, 0x51
MPP[36]	H32	CP_I2C1_SCK	3.3V, 2.2K PU
MPP[37]	F34	CP_I2C0_SCK	3.3V, 2.2K PU EEPROM 0x50, SPD 0x53
MPP[38]	H34	CP_I2C0_SDA	3.3V, 2.2K PU EEPROM 0x50, SPD 0x53
MPP[39]	F30	CP_MPP[39]	FAN_PWM_R
MPP[40]	F36	CP_SMI_MDIO	3.3V, 2.2K PU
MPP[41]	H36	CP_SMI_MDC	3.3V, 2.2K PU
MPP[42]	E39	CP_XSMI_MDC	3.3V, 2.2K PU, can replace CP_SMI_MDC by assembly option
MPP[43]	D30	CP_XSMI_MDIO	3.3V, 2.2K PU, can replace CP_SMI_MDIO by assembly option
MPP[44]	D38	CP_MPP[44]	3.3V, 10k PD, PCIe0 clock config
MPP[45]	A39	CP_MPP[45]	3.3V, 10k PD, Reset strap
MPP[46]	C37	CP_MPP[46]	3.3V, 10k PD, CPU Subsystem Clock CP0_SYS_PLL_SEL3
MPP[47]	A37	CP_MPP[47]	3.3V, 2.2k PD, Reset strap
MPP[48]	B40	CP_MPP[48]	3.3V, 10k PD, PCIe1 clock config
MPP[49]	B38	CP_MPP[49]	3.3V, 1k PD, can enable 1.8V supply for CP0:CP_VHV
MPP[50]	C35	CP_UA2_TXD	3.3V
MPP[51]	D34	CP_UA2_RXD	3.3V
MPP[52]	A35	CP_RCVR1_CLK/CP_RCVR2_CLK	3.3V, Recovered clock for SyncE
MPP[53]	B36	AP_VHV_EN	3.3V, 1k PD, can enable 1.8V supply for AP_VHV
MPP[54]	D36	CP_MPP[54]	3.3V, connected with ethernet phy clock output
MPP[55]	B34	CP_SD_CRD_DT	3.3V, 2.2k PU
MPP[56]	D32	CP_SD_CLK	3.3V (1.8V assembly option)
MPP[57]	B32	CP_SD_CMD	3.3V (1.8V assembly option)
MPP[58]	A33	CP_SD_D[0]	3.3V (1.8V assembly option)
MPP[59]	C33	CP_SD_D[1]	3.3V (1.8V assembly option)
MPP[60]	A31	CP_SD_D[2]	3.3V (1.8V assembly option)
MPP[61]	C31	CP_SD_D[3]	3.3V (1.8V assembly option)
MPP[62]	B30	NC	3.3V (1.8V assembly option)

CP1 MPP[0:62]

MPP #	Pin #	Pin Description	Notes
MPP[0]	AB21	NC	3.3V
MPP[1]	AC21	NC	3.3V
MPP[2]	AA22	NC	3.3V
MPP[3]	AA23	NC	3.3V
MPP[4]	AA21	NC	3.3V
MPP[5]	AB22	NC	3.3V
MPP[6]	AC18	NC	3.3V
MPP[7]	AB18	NC	3.3V
MPP[8]	AA19	NC	3.3V
MPP[9]	AA20	NC	3.3V
MPP[10]	AA18	NC	3.3V
MPP[11]	AB19	CP_MPP[11]	3.3V, BATLOW_N
MPP[12]	AA12	CP_MPP[12]	3.3V, SPKR
MPP[13]	AB13	CP_SPI1_MISO	3.3V, 2.2k PU
MPP[14]	AA17	CP_SPI1_CSn[0]	3.3V, 2.2k PU, for on-SoM TPM (assembly option)
MPP[15]	AA14	CP_SPI1_MOSI	3.3V, 10k PD
MPP[16]	AA13	CP_SPI1_SCK	3.3V, 10k PU
MPP[17]	AA8	CP_MPP[17]	3.3V, 2.2k PU, TPM PIRQ_N
MPP[18]	AA9	CP_MPP[18]	3.3V, Boot Mode[0]
MPP[19]	AB9	CP_MPP[19]	3.3V, Boot Mode[1]
MPP[20]	AB10	CP_MPP[20]	3.3V, Boot Mode[2]
MPP[21]	AA7	CP_MPP[21]	3.3V, Boot Mode[3]
MPP[22]	AC9	CP_MPP[22]	3.3V, Boot Mode[4]
MPP[23]	AB16	CP_MPP[23]	3.3V, Boot Mode[5]
MPP[24]	AA16	NC	3.3V
MPP[25]	AB15	CP_MPP[25]	3.3V, 2.2k PD, Reset strap
MPP[26]	AC15	CP_MPP[26]	3.3V, 2.2k PD, Reset strap
MPP[27]	AA10	NC	3.3V
MPP[28]	AA11	CP_PTP_PULSE	3.3V
MPP[29]	AC12	CP_PTP_CLK	3.3V
MPP[30]	AB12	CP_PTP_PCLK_OUT	3.3V
MPP[31]	AA15	NC	3.3V
MPP[32]	A9	NC	3.3V