CN9130 SOM Hardware User Manual

Revision and Notes

Date	Owner	Revision	Notes
26 Sep 2021	Alon Rotman	1.0	Initial release information 2. Relevant for PCB revision 1.0
24 Nov 2021	Alon Rotman	1.1
Oct 29,2023	Rabeeh Khoury	1.2	Added PCB rev 1.3 3D Model in Documentation section
Sep 02, 2024	Josua Mayer	1.3	Updated AP/CP Signal usage and B2B connectors tables according to production version SoM
Sep 10, 2024	Josua Mayer	1.3.1	Updated J3 SPI/USB signals
Sep 12, 2024	Josua Mayer	1.3.2	removed invalid mating connector part number for J3
Sep 16, 2024	Josua Mayer	1.3.3	added ptp signal descriptions
Dec 01, 2024	Josua Mayer	1.4	updated core clock signal descriptions to match pinout tables

No warranty of accuracy is given concerning the contents of the information contained in this publication. To the extent permitted by law no liability (including liability to any person by reason of negligence) will be accepted by SolidRun Ltd., its subsidiaries or employees for any direct or indirect loss or damage caused by omissions from or inaccuracies in this document. SolidRun Ltd. reserves the right to change details in this publication without prior notice. Product and company names herein may be the trademarks of their respective owners.

Introduction

This document is intended for hardware engineers that are willing to integrate the CN9130 SOM from SolidRun ltd, into their own design.

The document provides details with regards CN9130 SOM rev 1.1.

The CN9130 SOM is pin and size compatible to the A388 SOM by SolidRun and can be used as an upgrade for the existing ClearFog Base and ClearFog Pro.

Note: the pinout of the CN9130 and A388 are slightly different due to the MPP muxing of each SoC. please review carefully the tables below

Overview

CN9130 System On Module is a highly integrated SOM module based on Marvell’s CN9130 SoC.

The SoC highlights are up to 2.2GHz with 4 Cortex A72 Arm cores, DDR4 controller and 6 high speed SERDESs.

The module integrates the following features –

1. CN9130 SoC (up to 2.2GHz).

2. On board 64bit DDR4 bus supporting up to 16GB at 2400MT/s without ECC

3. Single 12V or 5V DC-input is required.

Block Diagram

Specifications

Features	CN9130 SOM Specifications
Processor Core	4 cores Arm Cortex A72
Processor speed	2.2GHz (Commercial) 2GHz (Industrial)
DDR	On board DDR4: Up to 16GB @ 2400MT/s 64bit (+ optional 8bit of ECC)
eMMC	Up to 64GB (assembled 8GB)
Flash	64Mbit SPI NOR flash
SATA 3.0	up to 2 Ports
Ethernet	1x MDI using 88E1512 PHY 1x 10/5 GbE port + 2x 1/2.5 GbE Ports or 2x 5 GbE Port +1x 1/2.5 GbE Port
PCIe gen 3.0	1 Port x4 + 2 Ports x 1 Total of 3 controllers and up to 6 lanes
USB 3.0	Up to 2 x USB 3.0 (Host/Device)
I2C	2
SMI & XSMI	2
UART	2
PPS/PTP/Sync-E support	Untested, for authoritative information, consult Marvell documentation and Errata (available under NDA).
SPI bus	✓
RTC support	✓
Power	5V to 12V DC-input 11.3W full system
Supported OS	Linux kernel 5.8x Yocto DPDK UEFI KVM/QEMU/Containers NFV Openstack compute node
Environment	Commercial: 0°C to 70°C Industrial: -40°C to 85°C Humidity (non-condensing): 10% – 90%
Dimensions	49mm X 35mm
	Buy Now

Compatibility between SOMs A388 and CN9130

Both SOMs have exactly the same form factor and footprint

The CN9130 SOM was designed to support SolidRun’s ClearFog Base/Pro. In case of any custom design based on A388 that wants to upgrade to CN9130, any case needs to be examined individually and review carefully the borad-to-board pinout

In the documentation section there is an excel table with exact pinout difference

Main differences due to SoC pinout:

Feature	A388	CN9130
USB2.0	3 Ports	2 Ports
SATA 3.0	3 Ports	2 Ports
125MHz clock out	✓	X
SD/EMMC Boot	boot from either SD or eMMC	Can boot from both SD or eMMC
MCi interface	X	✓ – Connector J3
input voltage	5V and 3.3V	5V

Power Consumption

The following power consumption measurements were conducted on the following setup:

1. Clearfog Pro carrier board

2. Voltage / current measurement on v_5v0 voltage rail

3. No mPCIe / USB / SATA / ETH cable were connected to the carrier board

4. Temperature measurement was taken from linux using the following command ‘cat /sys/class/thermal/thermal_zone?/temp’

5. Current and Voltage measured using an oscilloscope

6. Linux command ‘memtester 100M > /dev/null &’ ran 4 times according to core count

7. Linux command ‘cpuburn-krait’ is ran 4 times in background. The reason cpuburn-krait was chosen is since it can generate most heat out of the cores (the core pipeline are most utilized)

Frequency Scaling

In order to improve power efficiency and increase temperature limits, SolidRun had enabled cpu frequency scaling.

Please refer to the patch below for more information.

https://github.com/SolidRun/cn913x_build/commit/5fe77346371a230fd2468bfb11cbcc2c1ea10345

SolidRun, recommends to not disable the frequency scaling feature.

Power Measurments

The measurements below were conducted without frequency scaling, to reflect the maximum power consumption:

Test	Power [W]	Tj [degC]
Idle u-boot	4.6	50
idle Linux	4.08 4.2 4.7 5	53 65 90 105
memtester 64bit 2400MT/s	9.25 10.1 11.3	70 85 105
cpuburn-karit 4 cores at 2.2GHz	9.3 9.86 10.8	70 90 105

CN9130 SOM extensions

The CN9130 has two extension busses of high performance, low latency and low power Marvell® MoChi interfaces (MCi). Each bus is comprised of 4x high speed differential pairs and a dedicated LVDS clock. Both busses are exposed through the SOM connector, enabling to connect 1 or 2 additional 88F8215 comprising the kits of CN9131 and CN9132 on the carrier board and extending the SERDES count from 6 to 12 or 18.

SERDES Muxing CN9130 – CP0:

Interface	SERDES Lane0	SERDES Lane1	SERDES Lane2	SERDES Lane3	SERDES Lane4	SERDES Lane5
10GBASE-R/XFI			ETH_Port0		ETH_Port0
5GBASE-R			ETH_Port0		ETH_Port0 or ETH_Port1
10GBASE-X2 (RXAUI)			ETH_Port0 Lane 0	ETH_Port0 Lane 1	ETH_Port0 Lane0	ETH_Port0 Lane 1
1000BASE-X (SGMII) / 2.5GBASE-X (HS-SGMII)	ETH_Port1	ETH_Port2	ETH_Port0	ETH_Port1	ETH_Port0 or ETH_Port1	ETH_Port2
SATA 3.0	SATA1	SATA0	SATA0	SATA1		SATA1
USB 3.0 HOST		USB 3.0 Port0 Host	USB 3.0 Port0 Host	USB 3.0 Port1 Host	USB 3.0 Port1 Host
USB 3.0 Device		USB 3.0 Port0 Decive			USB 3.0 Port0 Decive
PCIe RC/EP	PCIex4 Port0 LANE0	PCIex4 Port0 LANE1	PCIex4 Port0 LANE2	PCIex4 Port0 LANE3	PCIex1 Port1	PCIex1 Port2
Assignment on Clearfog Base	SATA0 Port 1	USB-3.0 Host Port0	XFI ETH Port0	SGMII ETH Port1	USB-3.0 Host Port 1	PCIe Gen3 Port 2
Assignment on Clearfog Pro	SATA0 Port 1	USB-3.0 Host Port0	XFI ETH Port0	SGMII ETH Port1	PCIe Gen3 Port 1	PCIe Gen3 Port 2

The following port configuration can’t be used simultaneously:

• SGMII port 0 / HS SGMII port0, RXAUI and XFI/10GBASE

• SGMII port 1 and HS SGMII port 1

• SGMII port 2 and HS SGMII port 2

CORE Clock BOOT Straps

• PLL_SEL[0] – MPP[15] – CP_SPI1_MOSI

• PLL_SEL[1] – MPP[16] – CP_SPI1_SCK

• PLL_SEL[2] – MPP[17] – CP0_SYS_PLL_SEL2

• PLL_SEL[3] – MPP[46] (not exposed on B2B connector, 10K pull-down on SoM)

Core Clock [MHz]	Configuration PLL_SEL [3:0]
1600	0x0000 (0h0)
2000	0x0010 (0h2)
2200	0x0100 (0h4)

BOOT MODE BOOT Straps

• BOOT_MODE[0] – MPP18, 10K PU

• BOOT_MODE[1] – MPP19, 10K PU

• BOOT_MODE[2] – MPP20, 10K PD (not exposed on B2B connector)

• BOOT_MODE[3] – MPP21, 10K PU

• BOOT_MODE[4] – MPP22, 10K PU (not exposed on B2B connector)

• BOOT_MODE[5] – MPP23, 10K PU (not exposed on B2B connector)

BOOT MODE	Configuration BOOT_MODE [5:0]
SD Card (CP_SD)	0b101001 (0x29)
eMMC (AP_SD)	0b101010 (0x2A)
NOR Flash SPI 24 address bit (CP_SPI1)	0b110010 (0x32)
SD Card (CP_SD, undocumented)	0b111001 (0x39)
eMMC (AP_SD, undocumented)	0b111010 (0x3A)

CP0 MPP[62:0]

MPP #	Pin #	Pin Description	Notes
AP_MPP[0]	AP10	AP_SD_CLK	1.8V, serial 22ohm resistor
AP_MPP[1]	AT10	AP_SD_CMD	1.8V, 10K PU
AP_MPP[2]	AP16	AP_SD_D[0]	1.8V, 10K PU
AP_MPP[3]	AP18	AP_SD_D[1]	1.8V, 10K PU
AP_MPP[4]	AT16	AP_SD_D[2]	1.8V, 10K PU
AP_MPP[5]	AP14	AP_SD_D[3]	1.8V, 10K PU
AP_MPP[6]	AP12	AP_SD_DS	RCLK, 10K PD
AP_MPP[7]	AT14	AP_SD_D[4]	1.8V, 10K PU
AP_MPP[8]	AT12	AP_SD_D[5]	1.8V, 10K PU
AP_MPP[9]	AT18	AP_SD_D[6]	1.8V, 10K PU
AP_MPP[10]	AV18	AP_SD_D[7]	1.8V, 10K PU
AP_MPP[11]	AY18	AP_UA0_TXD	PD - Reset strap 3.3V thorough FXL2TD245L10X level shifter
AP_MPP[12]	BA17	AP_SD_HW_RST	1.8V, 10K PD
AP_MPP[19]	AW17	AP_UA0_RXD	3.3V thorough FXL2TD245L10X level shifter
MPP[0]	AY38	CP_SMI_MDIO	1.8V
MPP[1]	AV38	CP_SMI_MDC	1.8V
MPP[2]	AW39	CP_UA1_RXD	3.3V thorough FXL2TD245L10X level shifter
MPP[3]	AY40	CP_UA1_TXD	3.3V through FXL2TD245L10X level shifter
MPP[4]	AW41	CP_GPIO[4]	1.8V
MPP[5]	BA39	CP_GPIO[5]	1.8V
MPP[6]	AW35	CP_PTP_PULSE	1.8V
MPP[7]	AY36	CP_PTP_CLK	1.8V
MPP[8]	BA37	CP_PTP_PCLK_OUT	1.8V
MPP[9]	AW37	NC
MPP[10]	BA35	DDR_SPD_STRAP0	1.8V, PU ECC / PD No ECC
MPP[11]	AV36	DDR_SPD_STRAP1	1.8V, PU 8GB, PD 4GB
MPP[12]	AV32	CP_SPI1_CSn[1]	3.3V
MPP[13]	AY34	CP_SPI1_MISO	3.3V
MPP[14]	AT36	CP_SPI1_CSn[0]	3.3V
MPP[15]	AT32	CP_SPI1_MOSI	3.3V, CPU Subsystem Clock CP0_SYS_PLL_SEL0
MPP[16]	AV34	CP_SPI1_SCK	3.3V, CPU Subsystem Clock CP0_SYS_PLL_SEL1
MPP[17]	BA29	CP_GPIO[17]	3.3V, PD 50k, CPU Subsystem Clock CP0_SYS_PLL_SEL2
MPP[18]	AW29	CP_BOOT_MODE_SEL0	3.3V, Boot Mode[0]
MPP[19]	AV30	CP_BOOT_MODE_SEL1	3.3V, Boot Mode[1]
MPP[20]	BA31	CP_BOOT_MODE_SEL2	3.3V, Boot Mode[2]
MPP[21]	AT30	CP_BOOT_MODE_SEL3	3.3V, Boot Mode[3]
MPP[22]	AY30	CP_BOOT_MODE_SEL4	3.3V, Boot Mode[4]
MPP[23]	AP32	CP_BOOT_MODE_SEL5	3.3V, Boot Mode[5]
MPP[24]	AP34	NC
MPP[25]	AT34	CP_GPIO[25]	3.3V, Reset strap 2.2K PD
MPP[26]	AT38	CP_GPIO[26]	3.3V, Reset strap 10K PU
MPP[27]	AW31	CP_GPIO[27]	3.3V
MPP[28]	AY32	CP_GPIO[28]	3.3V
MPP[29]	BA33	CP_GPIO[29]	3.3V
MPP[30]	AW33	CP_GPIO[30]	3.3V
MPP[31]	AP36	CP_GPIO[31]	3.3V
MPP[32]	H30	CP_GPIO[32]	3.3V
MPP[33]	C39	CP_GPIO[33]	3.3V
MPP[34]	C41	CP_GPIO[34]	3.3V
MPP[35]	F32	CP_I2C1_SDA	3.3V, 2.2K PU
MPP[36]	H32	CP_I2C1_SCK	3.3V, 2.2K PU
MPP[37]	F34	CP_I2C0_SCK	3.3V, 2.2K PU EEPROM 0x53
MPP[38]	H34	CP_I2C0_SDA	3.3V, 2.2K PU EEPROM 0x53
MPP[39]	F30	CP_GPIO[39]	3.3V
MPP[40]	F36	CP_RCVR1_CLK	3.3V, 25MHz for SYNC-E connected to J1
MPP[41]	H36	VHV_EN	3.3V, 1K PD, can enable 1.8V supply for CP_VHV
MPP[42]	E39	NC
MPP[43]	D30	CP_SD_CRD_DT	3.3V
MPP[44]	D38	CP_GE2_TXD[2]	1.8V, Reset Strap
MPP[45]	A39	CP_GE2_TXD[3]	1.8V, Reset strap
MPP[46]	C37	CP_GE2_TXD[1]	1.8V, CPU Subsystem Clock CP0_SYS_PLL_SEL3, 10K PD
MPP[47]	A37	CP_GE2_TXD[0]	1.8V, Reset strap, 2.2K PD
MPP[48]	B40	CP_GE2_TXCTL	1.8V, Reset strap
MPP[49]	B38	CP_GE2_TXCLKOUT	1.8V, serial 22ohm resistor
MPP[50]	C35	CP_GE2_RXCLK	1.8V, serial 22ohm resistor
MPP[51]	D34	CP_GE2_RXD[0]	1.8V
MPP[52]	A35	CP_GE2_RXD[1]	1.8V
MPP[53]	B36	CP_GE2_RXD[2]	1.8V
MPP[54]	D36	CP_GE2_RXD[3]	1.8V
MPP[55]	B34	CP_GE2_RXCTL	1.8V
MPP[56]	D32	CP_SD_CLK	3.3V
MPP[57]	B32	CP_SD_CMD	3.3V
MPP[58]	A33	CP_SD_D[0]	3.3V
MPP[59]	C33	CP_SD_D[1]	3.3V
MPP[60]	A31	CP_SD_D[2]	3.3V
MPP[61]	C31	CP_SD_D[3]	3.3V
MPP[62]	B30	NC

SOM Header Details

Following are the SOM Connectors J1, J2, J3 pin mapping –

GND pins are marked with Red

The SOM has 3 connectors:

1. J1, J2 – DF40C-80DP-0.4V(51), 80 Mating connectors:

• DF40C-80DS-0.4V(51) – 1.5mm mating height

• DF40C(2.0)-80DS-0.4V(51) – 2mm mating height

• DF40C(4.0)-80DS-0.4V(51) – 4mm mating height

1. J3 – DF40C-70DP-0.4V(51), 70 Mating connectors:

• DF40C-70DS-0.4V(51) – 1.5mm mating height

• DF40C(2.0)-70DS-0.4V(51) – 2mm mating height

1. Spacers

• Manufacture PN: N0143416A (for 1.5mm stacking height)

• Screw M1.6

Connector J1

Notes	Driving IC	Schematics Pin Name	Pin Number	Pin Number	Schematics Pin Name	Driving IC	Notes
			2	1	GND (FIXED)
			4	3	MDI_P0	CP0 RGMII through 88E1512 PHY
3.3V	CP_MPP[40]	RCVR1_CLK_CP0	6	5	MDI_N0	CP0 RGMII through 88E1512 PHY
			8	7	GND (FIXED)
			10	9	MDI_P1	CP0 RGMII through 88E1512 PHY
			12	11	MDI_N1	CP0 RGMII through 88E1512 PHY
3.3V, 2.2K PU	CP_MPP[36]	I2C1_CP0_SCL	14	13	GND (FIXED)
3.3V	CP_MPP[12]	SPI1_CP0_CS1_N	16	15	MDI_P2	CP0 RGMII through 88E1512 PHY
3.3V	CP_MPP[29]	CP0_GPIO2	18	17	MDI_N2	CP0 RGMII through 88E1512 PHY
3.3V thorough NTB0102GD level shifter, 2.2K PU	CP_MPP[2]	UART1_CP0_RX	20	19	GND (FIXED)
3.3V	CP_MPP[30]	CP0_GPIO3	22	21	MDI_P3	CP0 RGMII through 88E1512 PHY
3.3V thorough NTB0102GD level shifter, 2.2K PU	CP_MPP[3]	UART1_CP0_TX	24	23	MDI_N3	CP0 RGMII through 88E1512 PHY
		GND (FIXED)	26	25	GND (FIXED)
1.8V	CP_MPP[5]	CP0_GPIO9_1.8V	28	27	PHY0_RST_N_1.8V		1.8V, input reset to PHY
3.3V, Reset Strap	CP_MPP[18]	CP0_BOOT_MODE_SEL0	30	29	GBE0_LED2_INT_N_1.8V	88E1512	1.8V, serial 510ohm resistor
3.3V, Reset Strap	CP_MPP[19]	CP0_BOOT_MODE_SEL1	32	31	GBE0_LED1_1.8V	88E1512	1.8V, serial 510ohm resistor
3.3V, Reset Strap	CP_MPP[21]	CP0_BOOT_MODE_SEL3	34	33	GBE0_LED0_1.8V	88E1512	1.8V, serial 510ohm resistor
SD CARD, 3.3V, 2.2K PU	CP_MPP[43]	SD_CP0_CD_N	36	35	SMI_CP0_MDIO	CP_MPP[0]	1.8V, 2.2K PU, connected to PHY 88E1512 ADD 0x0
3.3V thorough NTB0102GD level shifter, 2.2K PU	AP_MPP[19]	UART_AP_RX0	38	37	SMI_CP0_MDC	CP_MPP[1]	1.8V, 2.2K PD (Reset Strap), connected to PHY 88E1512 ADD 0x0
3.3V thorough NTB0102GD level shifter, 2.2K PU	AP_MPP[11]	UART_AP_TX0	40	39	POWER_OFF_N		1.8V
Reset IN 3.3V, 2.2K PU		SYS_RESET_N	42	41	GND (FIXED)
			44	43	JTAG_CP0_TCK		JTAG, 3.3V, 10K PD
Reset OUT 3.3V, 2.2K PU		CP0_SYSRST_OUT_N	46	45	JTAG_CP0_TRST_N		JTAG, 3.3V, 10K PD
			48	47	JTAG_CP0_TDI		JTAG, 3.3V, 10K PU
JTAG, 3.3V, 10K PU		JTAG_CP0_TMS	50	49	JTAG_CP0_TDO		JTAG, 3.3V, 10K PU
			52	51	CP0_GPIO0	CP_MPP[27]	3.3V
SD CARD, 3.3V	CP_MPP[58]	SD_CP0_SDIO_D0	54	53	SD_CP0_SDIO_CMD	CP_MPP[57]	SD CARD, 3.3V
SD CARD, 3.3V	CP_MPP[61]	SD_CP0_SDIO_D3	56	55	SD_CP0_SDIO_CLK	CP_MPP[56]	SD CARD, 3.3V
		GND (FIXED)	58	57	CP0__GPIO1	CP_MPP[28]	3.3V
SD CARD, 3.3V	CP_MPP[59]	SD_CP0_SDIO_D1	60	59	GND (FIXED)
SD CARD, 3.3V	CP_MPP[60]	SD_CP0_SDIO_D2	62	61	I2C1_CP0_SDA	CP_MPP[35]	3.3V, 2.2K PU
			64	63
3.3V, 2.2K PU, EEPROM 0x53	CP_MPP[38]	I2C0_CP0_SDA	66	65
3.3V, 2.2K PU, EEPROM 0x53	CP_MPP[37]	I2C0_CP0_SCL	68	67
1.8V	CP_MPP[6]	PTP_CP0_PULSE_1.8V	70	69	VIN		12V or 5V
1.8V	CP_MPP[7]	PTP_CP0_CLK_IN_1.8V	72	71	VIN		12V or 5V
1.8V	CP_MPP[8]	PTP_CP0_PCLK_OUT_1.8V	74	73	VIN		12V or 5V
1.8V	CP_MPP[4]	CP0_GPIO8_1.8V	76	75	VIN		12V or 5V
		GND (FIXED)	78	77	VIN		12V or 5V
			80	79	VIN		12V or 5V

Connector J2

Notes	Driving IC	Schematics Pin Name	Pin Number	Pin Number	Schematics Pin Name	Driving IC	Notes
No on-board serial capacitor		B2B_SRD2_TX_P	2	1	GND (FIXED)
No on-board serial capacitor		B2B_SRD2_TX_N	4	3	USB2_CP0_DP1
		GND (FIXED)	6	5	USB2_CP0_DM1
No on-board serial capacitor		B2B_SRD2_RX_P	8	7	GND (FIXED)
No on-board serial capacitor		B2B_SRD2_RX_N	10	9
		GND (FIXED)	12	11
No on-board serial capacitor		B2B_SRD4_RX_P	14	13	GND (FIXED)
No on-board serial capacitor		B2B_SRD4_RX_N	16	15	USB2_CP0_DP0
		GND (FIXED)	18	17	USB2_CP0_DM0
No on-board serial capacitor		B2B_SRD4_TX_P	20	19	CP0_GPIO4	CP_MPP[31]	3.3V
No on-board serial capacitor		B2B_SRD4_TX_N	22	21
		GND (FIXED)	24	23	3.3V_RTC_B2B		3.3V battery voltage
No on-board serial capacitor		B2B_SRD1_TX_P	26	25	PCIE_REFCLK_N1		100MHz HCSL clock out, no serial capacitors
No on-board serial capacitor		B2B_SRD1_TX_N	28	27	PCIE_REFCLK_P1		100MHz HCSL clock out, no serial capacitors
		GND (FIXED)	30	29	GND (FIXED)
No on-board serial capacitor		B2B_SRD1_RX_P	32	31	PCIE_REFCLK_P0		100MHz HCSL clock out, no serial capacitors
No on-board serial capacitor		B2B_SRD1_RX_N	34	33	PCIE_REFCLK_N0		100MHz HCSL clock out, no serial capacitors
		GND (FIXED)	36	35	GND (FIXED)
No on-board serial capacitor		B2B_SRD5_RX_P	38	37
No on-board serial capacitor		B2B_SRD5_RX_N	40	39
		GND (FIXED)	42	41
No on-board serial capacitor		B2B_SRD5_TX_P	44	43	CP0_SYS_PLL_SEL2	CP_MPP[17]	3.3V, PD 50k, Boot strap
No on-board serial capacitor		B2B_SRD5_TX_N	46	45	CP0_GPIO5	CP_MPP[32]	3.3V
		GND (FIXED)	48	47	CP0_GPIO7	CP_MPP[34]	3.3V
No on-board serial capacitor		B2B_SRD3_TX_P	50	49
No on-board serial capacitor		B2B_SRD3_TX_N	52	51
		GND (FIXED)	54	53	GND (FIXED)
No on-board serial capacitor		B2B_SRD3_RX_P	56	55
No on-board serial capacitor		B2B_SRD3_RX_N	58	57	CP0_GPIO6	CP_MPP[33]	3.3V
		GND (FIXED)	60	59
No on-board serial capacitor		B2B_SRD0_RX_P	62	61
No on-board serial capacitor		B2B_SRD0_RX_N	64	63	1.8V_VHV		NC
		GND (FIXED)	66	65	1.8V_OUT		Option to provide 1.8V out for low power misc logic
No on-board serial capacitor		B2B_SRD0_TX_P	68	67	1.8V_OUT		Option to provide 1.8V out for low power misc logic
No on-board serial capacitor		B2B_SRD0_TX_N	70	69
		GND (FIXED)	72	71	PHY_CLK125_OUT
			74	73	CP0_MPP39	CP_MPP[39]	3.3V
			76	75
3.3V	CP_MPP[13]	SPI1_CP0_MISO_M	78	77	SPI1_CP0_MOSI_M	CP_MPP[15]	3.3V, Boot Strap
3.3V	CP_MPP[14]	SPI1_CP0_CS0_N	80	79	SPI1_CP0_CLK_M	CP_MPP[16]	3.3V, Boot Strap

Connector J3

Notes	Driving IC	Schematics Pin Name	Pin Number	Pin Number	Schematics Pin Name	Driving IC	Notes
		GND (FIXED)	2	1	GND (FIXED)
No on-board serial capacitor		AP_MCI0_RX_CP1_N2	4	3	AP_MCI0_TX_CP1_P0		No on-board serial capacitor
No on-board serial capacitor		AP_MCI0_RX_CP1_P2	6	5	AP_MCI0_TX_CP1_N0		No on-board serial capacitor
		GND (FIXED)	8	7	GND (FIXED)
No on-board serial capacitor		AP_MCI0_RX_CP1_N1	10	9	REFCLK_MCI0_CP1_N		No on-board serial capacitor
No on-board serial capacitor		AP_MCI0_RX_CP1_P1	12	11	REFCLK_MCI0_CP1_P		No on-board serial capacitor
		GND (FIXED)	14	13	GND (FIXED)
No on-board serial capacitor		AP_MCI0_RX_CP1_N0	16	15	AP_MCI0_TX_CP1_P1		No on-board serial capacitor
No on-board serial capacitor		AP_MCI0_RX_CP1_P0	18	17	AP_MCI0_TX_CP1_N1		No on-board serial capacitor
		GND (FIXED)	20	19	GND (FIXED)
No on-board serial capacitor		AP_MCI0_RX_CP1_P3	22	21	AP_MCI0_TX_CP1_P2		No on-board serial capacitor
No on-board serial capacitor		AP_MCI0_RX_CP1_N3	24	23	AP_MCI0_TX_CP1_N2		No on-board serial capacitor
		GND (FIXED)	26	25	GND (FIXED)
Drive high for muxing SoM SPI FLash to J3-SPI_B2B_*	SPI Mux	SEL_SPI_MUX	28	27	AP_MCI0_TX_CP1_P3		No on-board serial capacitor
controlled by SEL_SPI_MUX	SoM SPI Flash	SPI_B2B_CS0_N	30	29	AP_MCI0_TX_CP1_N3		No on-board serial capacitor
No on-board serial capacitor		GND (FIXED)	32	31	GND (FIXED)
controlled by SEL_SPI_MUX	SoM SPI Flash	SPI_B2B_CLK	34	33
controlled by SEL_SPI_MUX	SoM SPI Flash	SPI_B2B_MOSI	36	35			Connected to on board STM32 for management
controlled by SEL_SPI_MUX	SoM SPI Flash	SPI_B2B_MISO	38	37			3.3V, connected to EFUSE
		GND (FIXED)	40	39	GND (FIXED)
Not connected since v1.1		USB_MCU_DP	42	41	AP_MCI1_TX_CP2_P3		No on-board serial capacitor
Not connected since v1.1		USB_MCU_DM	44	43	AP_MCI1_TX_CP2_N3		No on-board serial capacitor
		GND (FIXED)	46	45	GND (FIXED)
No on-board serial capacitor		AP_MCI1_RX_CP2_P0	48	47	AP_MCI1_TX_CP2_N0		No on-board serial capacitor
No on-board serial capacitor		AP_MCI1_RX_CP2_N0	50	49	AP_MCI1_TX_CP2_P0		No on-board serial capacitor
		GND (FIXED)	52	51	GND (FIXED)
No on-board serial capacitor		AP_MCI1_RX_CP2_P1	54	53	REFCLK_MCI1_CP2_N		No on-board serial capacitor
No on-board serial capacitor		AP_MCI1_RX_CP2_N1	56	55	REFCLK_MCI1_CP2_P		No on-board serial capacitor
		GND (FIXED)	58	57	GND (FIXED)
No on-board serial capacitor		AP_MCI1_RX_CP2_P3	60	59	AP_MCI1_TX_CP2_P1		No on-board serial capacitor
No on-board serial capacitor		AP_MCI1_RX_CP2_N3	62	61	AP_MCI1_TX_CP2_N1		No on-board serial capacitor
		GND (FIXED)	64	63	GND (FIXED)
No on-board serial capacitor		AP_MCI1_RX_CP2_N2	66	65	AP_MCI1_TX_CP2_N2		No on-board serial capacitor
No on-board serial capacitor		AP_MCI1_RX_CP2_P2	68	67	AP_MCI1_TX_CP2_P2		No on-board serial capacitor
		GND (FIXED)	70	69	GND (FIXED)

Heatsink

SolidRun provides few types of heatsinks:

1. Cool-plate: flattens the surface of the SOM, making it easier for integration in any enclosure design

2. Evaluation heatsink: add-on for the cool-plate, with short ribs, enabling to mount a 40mmX40mm fan. This heatsink is to be used in open frame systems, to enable developers to work with the CN9130 SOM during bring-up and software development

Precision Time Protocol (PTP)

Note: Information on PTP is based on SoM schematics and SoC datasheet analysis, but actual functionality has not been tested. For authoritative information, consultation of Marvell documentation and Errata (available under NDA) is strongly recommended.

CN9130 SoC has hardware support for PTP* and Synchronous Ethernet*.

There are three related electrical signals:

1. PTP_PULSE (IN/OUT): Pulse per second. Muxable to J1-57 (MPP[28])

2. PTP_CLK (IN/OUT) @ J1-18 (MPP[29]), J2-73 (MPP): Discrete trigger using Generate function. Muxable to J1-18 (MPP[29]), J2-73 (MPP[39])

3. PTP_PCLK_OUT (OUT): Recovered clock output. Muxable to J1-22 (MPP[30])

PTP_PULSE and PTP_CLK can each synchronise between master and slave, the former generating periodic pulses while the latter depends on external events such as Update and Generate.

The PTP reference clock is generated internally.

PCLK_OUT provides the recovered clock, generated from a serdes lane according to its configuration registers.

Enable PTP on Clearfog Base / Pro

Note: Information on PTP is based on SoM schematics and SoC datasheet analysis, but actual functionality has not been tested. For authoritative information, consult Marvell documentation and Errata (available under NDA).

Clearfog Base / Pro support the mentioned PTP signals on the mikroBus connector:

• PTP_PULSE: U14-2 / U3-2 “RST”

• PTP_CLK: U14-9 / U3-9 “PWM”

• PTP_PCLK_OUT: U14-10 / U3-10 “INT”

By default these are acting as GPIOs, apply the device-tree changes below to select PTP:

diff --git a/arch/arm64/boot/dts/marvell/cn9130-cf-base.dts b/arch/arm64/boot/dts/marvell/cn9130-cf-base.dts
index 788a5c302b17..d93ad507ac24 100644
--- a/arch/arm64/boot/dts/marvell/cn9130-cf-base.dts
+++ b/arch/arm64/boot/dts/marvell/cn9130-cf-base.dts
@@ -136,7 +136,7 @@ led@1 {
 };
 
 &cp0_pinctrl {
-	pinctrl-0 = <&sim_select_pins>;
+	pinctrl-0 = <&ptp_pins>, <&sim_select_pins>;
 	pintrl-names = "default";
 
 	rear_button_pins: cp0-rear-button-pins {
diff --git a/arch/arm64/boot/dts/marvell/cn9130-cf.dtsi b/arch/arm64/boot/dts/marvell/cn9130-cf.dtsi
index ad0ab34b6602..240e298e897a 100644
--- a/arch/arm64/boot/dts/marvell/cn9130-cf.dtsi
+++ b/arch/arm64/boot/dts/marvell/cn9130-cf.dtsi
@@ -123,6 +123,8 @@ &cp0_pcie2 {
 };
 
 &cp0_pinctrl {
+	pinctrl-0 = <&ptp_pins>;
+
 	cp0_i2c1_pins: cp0-i2c1-pins {
 		marvell,pins = "mpp35", "mpp36";
 		marvell,function = "i2c1";
@@ -134,6 +136,11 @@ cp0_mmc0_pins: cp0-mmc0-pins {
 		marvell,function = "sdio";
 	};
 
+	ptp_pins: cp0-ptp-pins {
+		marvell,pins = "mpp28", "mpp30", "mpp39";
+		marvell,function = "ptp";
+	};
+
 	mikro_spi_pins: cp0-spi1-cs1-pins {
 		marvell,pins = "mpp12";
 		marvell,function = "spi1";

PTP is supported by the CN9130 Linux Etherent Controller Driver “MVPP2”, ensure to enable it’s kernel config option CONFIG_MVPP2_PTP: https://github.com/torvalds/linux/blob/master/drivers/net/ethernet/marvell/Kconfig#L97

Documentation

2MB

cn9130_som_rev1.1-simplified schematics.pdf

PDF

Open

512KB

CN9130-som-heatsink-files.zip

archive

Open

21KB

B2B pinout A388 and CN9130.xlsx

Open

1MB

CN9130-SOM-Mechanical-Files.zip

archive

Open

2MB

CN9130_SOM_REV1.1_STEP.zip

archive

Open

614KB

Reliability prediction for CN9130 SOM V1.pdf

PDF

Open

2MB

CN9130_SOM_REV1.3_3D.zip

archive

Open

Buy a Sample Now